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Forum: FPGA, VHDL & Verilog


Programmable logic


Subject Author Replies Last post
sticky FPGA development resources Andreas S. 15
Adaptive huffman algorithm in vhdl Robin 3
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Modelsim Altera verilog Error state emory exceed but i'm pretty sure there's plenty of space left Steve W. 0
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Please provide source code Mayank 11
Digital Clock Manager Divya P. 3
high impedance use others Daniel C. 2
Creating csync for external pixelbus Joey O. 6
Help with system description Daniel C. 13
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VHDL: BCD to Sevensegment Tobias Hagenaars 7
RCA Testbench returns XXXXXXXX for 32 bit adder Hakim M. 3
The never seen SBC + FPGA board- VAAMAN! Vicharak 1
ModelSim memory allocation failure FPGA guy 11
How to add two signals of type std_logic Ashok M. 6
Interfacing 4x4 keypad with 16x2 LCD on FPGA using VHDL Sebastian M. 1
How to implement lookup table in VHDL Were to lookup? 7
Adding a Reset reduces used LE's by 35% Karsten F. 23
gnerating data flow diagrams from c code James Yunker 6
Verilog Code for 4 32 bit numbers sorting in Ascending order Chaitanya Bommu 15
How to use FPGA to drive TFT LCD Cliff W. 11
Synchronous two PWM signals generator Stas I. 3
Optimising size and speed Muhammad Tahir R. 5
I need to clarify a question about verilog Black 6
HELP- VHDL model of the PULSE TIMER Sandra L. 2
Read Bitmap Color depth 4 Bits Guest 6
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package and procedure Dang T. 2
Executing ONERROR command at macro ./halfadder_simu.do line 6 RAMA 1
Error loading design (Modelsim student version) Keltuzad 64
Types do not match between component and entity at Simulation on Modelsim Nima 8
vcom-1576 error with expecting BEGIN SilentRoar 5
*HELP VHDL CODE * MariosBon 19
Help creating a SPI state machine in VHDL Michael N. 2
Led matrix VHDL Nathex 12
HELP-VHDL-CODE Merima D. 7
Microsemi Smartfusion2 i²C Setup Allfred 0
unexpected behavior of non-blocking assignment in an priority arbiter Jimmy Z. 5
Error creating Nios II application and BSP from template Nasas Kycas 7
washing machine (fsm) controller Jad F. 5
Knight Rider VHDL Elton Saraçi 3
Display binary image on vga using VHDL ElectroCataru 5
Index Input for Encoder Interface SparkyT 11
Compile warnings in model sim Peter Reitinger 4
SDRAM read problem 94onur94 1
get some outputsignals if cnt reaches an exact amount Steven Tumler 2
Initializing simulation with data from ILA Poor and lonely unused sequential element 2