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Forum: FPGA, VHDL & Verilog


Programmable logic


Subject Author Replies Last post
sticky FPGA development resources Andreas S. 15
Where is the fatal error? I couldnt find it Engin 14
error (12007) top-level design entity "projet" is undefined Lpsyco Lpsyco 5
How to generate a few clocks at ModelSim Electrical_Student 3
Help with Terms in .V file bteddy 6
How to check the value of a specific bit in vhdl NINA 4
Ring oscillator timing simulation Chris C1111 24
Puls generation at specific points in time Gerhard K. 13
i have this school task on vhdl code using xlinx and i don't know how to fix this code. Hiii D. 3
VHDL error issue "Static elaboration of top level VHDL design unit in library work failed." abith itty jacob 3
Getting Rank of Elements in an Array Md B. 4
Sequential Operations and resource sharing Carlos 5
2D Platforming logic for a Verilog FPGA game Umar H. 0
Memory Address Register not outputing the input Mahmoud R. 2
Learing Verilog help Kevin S. 4
ABEL to Verilog conversion Sutton Mehaffey 6
FPGA pin multiple usage SparkyT 6
Flashing digits from 0 to 9 Ber 25 5
Making a frequency reducer Eric J. 6
Error when running modelsim Mart Bent 7
Help not working properly daniel 2
floating point result is wrong Onur 2
Clock frequency reducer Eric J. 3
johnson counter VhdlTest V. 2
Counter with overflow signal at 1001 Eric J. 1
Converting binary number to seven-segment-display Eric J. 1
Making a counter using VHDL Eric J. 2
vhdl input clock to output Chris MiTo 4
4bit counter with load test bench fail Christos Goulas 8
Programming OR and XNOR with 4 inputs using functions NMV 2
Binary counter daniel 3
help in reading a large text file using verilog. Alangs Kannan 19
VHDL Guitar Effects "Pedal" Daniel 12
Accessing dut variables in testbench : VHDL Muhammad Tahir R. 4
Calculator from keyboard display 7seg Ali R. 10
Adaptive huffman algorithm in vhdl Robin 3
U250 flashing unsuccessful Pi N. 0
connecting components together Durko Rurko 1
VexRiscV system with GDB-Server in Hardware BLangOS 4
Modelsim Altera verilog Error state emory exceed but i'm pretty sure there's plenty of space left Steve W. 0
simulation in gowin fpga designer Mozhgan R. 3
Please provide source code Mayank 11
Digital Clock Manager Divya P. 3
high impedance use others Daniel C. 2
Creating csync for external pixelbus Joey O. 6
Help with system description Daniel C. 13
Interfacing Nexys2 FPGA with DAC8811 - coding issue Divya P. 5
VHDL: BCD to Sevensegment Tobias Hagenaars 7
RCA Testbench returns XXXXXXXX for 32 bit adder Hakim M. 3
The never seen SBC + FPGA board- VAAMAN! Vicharak 1
ModelSim memory allocation failure FPGA guy 11
How to add two signals of type std_logic Ashok M. 6