Forum: FPGA, VHDL & Verilog

Programmable logic

Subject Author Replies Last post
sticky FPGA development resources Andreas S. 6
One big module vs multiple small? Mark L. 7
is it possible for bcd to ascii module? John B. 3
coding at gate level? Mark L. 5
Verilog For Counter: How to store 32 bit counter values as 4 8-bit registers ? Saraswathy S. 9
LRM. 10.4.2 non blocking synthesis Mark L. 3
Record port map in VHDL New 3
Cpu: why only on posedge? Mark L. 6
Post-synthesis simulation, Quartus and Modelsim-Altera Reza M. Shahshahani 7
Task in verilog for sending the responses for respective address Sushma K. 2
I am thinking a FPGA design with video capture Vincent Y. 3
Clear_preset flip flop inputs BK_Coder 2
OS on a fpga Mark L. 12
How to generate Trigger for 500ns in Verilog ? Saraswathy S. 0
initializing oled display using vhdl Alex H. 2
Designated Number Counter and Cycle counter 2 Digit Jason Wang 13
SPI slave design idea? Jack BK 24
FT4222H Problem avi 1
Interfacing ADC with FPGA Varun Chitransh 3
Simulink Voltage-to-Frequency Converter on matlab. Bùi Cường 3
oscillator 50MHz Dima Potapov 5
New to VHDL Need help with this assignment James Yang 8
APA102 led strip with altera DE2-115 Board Peter 3
Quartus II TCL script to try multiple fitter seed settings? andi6510 4
flop-flop simulation in ModelSim Dima Potapov 19
is at left hand side of signal assignment statement. Wilson Torres 1
Control brightness of LEDs using VHDL Tanjila Tahsin 1
16-bit ALU from 1- bit ALU Mitsos Mitsos 2
Syntax Error Rectification Rejoy Mathews 0
Microprocessor Datapath FSM Controller Ed Hower 0
Xilinx Custom IP accessing 16-bit bram gundamz2001 2
Learning FPGA DE10 Nano Nirav Shah 3
ADC on DEO NANO not working chinmaye 3
locked HELP VHDL code for ADC at FPGA vicky d. 13
Verilog Data Type Rejoy Mathews 2
what is this ? Ritesh Kakkar 6
ERROR:HDLCompiler:1440 : Non-constant loop condition not supported for for TienNguyen 4
Verilog task yield "x" for a variable in a timestep Frank Li 4
FPGA image fusion & stereo vision Karamazov 1
bits_counter meido 4
Width Mismatch in RAM Design Ed Hower 5
Verilog code for modulus of negative number query Lakshita Jaiswal 3
Verilog Query Jay 5
cheap fpga for starting Sylvana Windrunner 13
VHDL UART how to handle incoming bytes? Macellan Macellan 0
Implement function for three architectures using VHDL Sergey Levko 1
Controlling the tasks Sushma K S 0
IP with axi-stream slave and axi4-full master interface zyed 1
VIVADO IP integration Elico C. 0
verilog Voltage Control Oscillator Rock Bog 3
GSoC Applications Window Closes on 27.03.18. Rex Or 0