Forum: FPGA, VHDL & Verilog

Programmable logic

Subject Author Replies Last post
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Adding a Reset reduces used LE's by 35% Karsten F. 23
gnerating data flow diagrams from c code James Yunker 6
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Synchronous two PWM signals generator Stas I. 3
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HELP- VHDL model of the PULSE TIMER Sandra L. 2
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Executing ONERROR command at macro ./halfadder_simu.do line 6 RAMA 1
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Types do not match between component and entity at Simulation on Modelsim Nima 8
vcom-1576 error with expecting BEGIN SilentRoar 5
*HELP VHDL CODE * MariosBon 19
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unexpected behavior of non-blocking assignment in an priority arbiter Jimmy Z. 5
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Compile warnings in model sim Peter Reitinger 4
SDRAM read problem 94onur94 1
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Initializing simulation with data from ILA Poor and lonely unused sequential element 2