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Forum: FPGA, VHDL & Verilog


Programmable logic


Subject Author Replies Last post
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Verilog Code for 4 32 bit numbers sorting in Ascending order Chaitanya Bommu 15
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I need to clarify a question about verilog Black 6
HELP- VHDL model of the PULSE TIMER Sandra L. 2
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package and procedure Dang T. 2
Executing ONERROR command at macro ./halfadder_simu.do line 6 RAMA 1
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Types do not match between component and entity at Simulation on Modelsim Nima 8
vcom-1576 error with expecting BEGIN SilentRoar 5
*HELP VHDL CODE * MariosBon 19
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unexpected behavior of non-blocking assignment in an priority arbiter Jimmy Z. 5
Error creating Nios II application and BSP from template Nasas Kycas 7
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Index Input for Encoder Interface SparkyT 10
Compile warnings in model sim Peter Reitinger 4
SDRAM read problem 94onur94 1
get some outputsignals if cnt reaches an exact amount Steven Tumler 2
Initializing simulation with data from ILA Poor and lonely unused sequential element 2
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Clock domain crossing Stefania M. 7
VHDL Blinking leds James H. 2
gps nmea design using verilog Dammrr R. 11
counter with signal enable (active high) and synchronous reset signal (active high) Juan 2
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Double Data Rate Serializer verilog Atalin 3
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Abel to VHDL Jose 3
Image processing in Verilog - simulation yk_learner 2
is it possible for bcd to ascii module? John B. 8
for loop in verilog code nelson george 20
Verilog: # Error loading design Vasily D. 1
Can anyone help me to solve this verilog(beginner) question or suggest me any source for solving Omar K. 1
beginner question on gate level d flip flop simulation Jimmy Z. 1
ice40HX8k enable signal from clock Fabian 1
How to properly multiply signed and unsigned signed unsigned 1
Synthesis: Mix of sync and async assignments to register if else what when 5
Determining trace delay for input delay constraints Timing violation 13
Enhanced Tiger Single Board Computer Myron P. 3
Getting to the Root Cause of BGA Assembly Problems smartronics 1