EmbDev.net

Forum: FPGA, VHDL & Verilog


Programmable logic


Subject Author Replies Last post
sticky FPGA development resources Andreas S. 6
12 Hour Clock problem PAUL W. 1
help in reading a large text file using verilog. Alangs Kannan 15
Weird warning for my design dayana42200 17
I don't understand this Aldemaro G. 5
ERROR - Design is empty yasoua 4
Verilog start daniels 1
Conceptual help needed Mike P. 1
Counter and Alter FIFO using VHDL/Verilog Saraswathy S. 2
convert number Verilog Sergei C. 2
Accelerating ODE solving with FPGA Madu 0
DigiAsic ACB2CA Dev Board Paul B. 1
Import package error system Verilog Nikhil Ghanathe 3
DIGIASIC Cyclone II Development Board Info Mehrdad T. 4
More toggles than expected. bob 4
Verilog Simple SPI Code? Ferhat YOL 14
facing intra clock path setup violations jose 0
How make memset funciotion on vhdl? Martin F. 1
Error Loading Design Model Sim PE student edition 10.1 Amit Ram S. 9
CAN controller implementation using FPGA CJU 8
One big module vs multiple small? Mark L. 7
is it possible for bcd to ascii module? John B. 3
coding at gate level? Mark L. 5
Verilog For Counter: How to store 32 bit counter values as 4 8-bit registers ? Saraswathy S. 9
LRM. 10.4.2 non blocking synthesis Mark L. 3
Record port map in VHDL New 3
Cpu: why only on posedge? Mark L. 6
Post-synthesis simulation, Quartus and Modelsim-Altera Reza M. Shahshahani 7
Task in verilog for sending the responses for respective address Sushma K. 2
I am thinking a FPGA design with video capture Vincent Y. 3
Clear_preset flip flop inputs BK_Coder 2
OS on a fpga Mark L. 12
How to generate Trigger for 500ns in Verilog ? Saraswathy S. 0
initializing oled display using vhdl Alex H. 2
Designated Number Counter and Cycle counter 2 Digit Jason Wang 13
SPI slave design idea? Jack BK 24
FT4222H Problem avi 1
Interfacing ADC with FPGA Varun Chitransh 3
Simulink Voltage-to-Frequency Converter on matlab. Bùi Cường 3
oscillator 50MHz Dima Potapov 5
New to VHDL Need help with this assignment James Yang 8
APA102 led strip with altera DE2-115 Board Peter 3
Quartus II TCL script to try multiple fitter seed settings? andi6510 4
flop-flop simulation in ModelSim Dima Potapov 19
is at left hand side of signal assignment statement. Wilson Torres 1
Control brightness of LEDs using VHDL Tanjila Tahsin 1
16-bit ALU from 1- bit ALU Mitsos Mitsos 2
Syntax Error Rectification Rejoy Mathews 0
Microprocessor Datapath FSM Controller Ed Hower 0
Xilinx Custom IP accessing 16-bit bram gundamz2001 2
Learning FPGA DE10 Nano Nirav Shah 3
ADC on DEO NANO not working chinmaye 3