Forum: FPGA, VHDL & Verilog

Programmable logic

Subject Author Replies Last post
sticky FPGA development resources Andreas Schwarz 5
Connecting Several Modules and a USB Christopher Brissette 0
VHDL Code error Hareesh Mohanan 6
Benfits of Soc FPGA Abdeljalil 1
Internal signals in vhdl Hareesh Mohanan 7
FPGA VS CPU Comparaison Abdeljalil 9
Verilog with FSM Rytis 2
FPGA - DL & ML jimmy 0
FPGA Tasks to do Jnine 2
VHDL instantiation in modelSim Hareesh Mohanan 10
MAC architecture (adder / accumulator) 16 bits Pollyana 4
verilog code for vending machine for given document vamshi 2
Error creating Nios II application and BSP from template Nasas Kycas 5
VHDL coding Register assignment Hareesh Mohanan 3
Artificial Neural Network in FPGA Andrzej Borucki 3
What is pin of primary clock in Lattice XP2 ? Mikas Petrauskas 1
FPGA gpio pin Hareesh Mohanan 4
Findign max value in continuous data stream Macellan Macellan 3
FSM: a state gets latched Daniel 1
How to get current time in FPGA? LisaLLLL 4
constrain implementation Sophie Ttazeaee 4
Viterbi Decoder Julian Mortimer 0
Wrong syntax near Cergey Chaulin 1
Xilinx BRAM behaviour query. Julian Mortimer 0
Problem synthesizing in Vivado Julian Mortimer 4
Xilinx's RAM Joey Weyland 0
Interfacing rotary encoder with Spartan 3 E Nirav Bhatt 0
Connect FPGA with i2c to a mikrocontroller ki92 2
Implementing Recast block in FPGA. Japa 1
send UDP packets from FPGA meleneemil 15
ERROR:HDLCompiler:1440 : Non-constant loop condition not supported for for TienNguyen 2
UCF Motor Stepper On FPGA SPARTAn 3E with Driver L 293 Freddy Silaban 12
Excess 3 to gray code using verilog Kamal 0
Use of rotary encoder in Spartan 3E Nirav Bhatt 2
RTL technique about "for" combine murakami 1
LVDS Controller LCD Panel nairolf_sch 2
Use I2C Core on DE0? Mo 1
qsys and user design mike 2
Assignment under elsif does not work Burak Güneş 6
Programmable SoC and SoC FPGA Abdeljalil Bounaime 1
locked Interleaver/deinterleaver VHDL Syed Imam 9
NAND with x input LE DUC LOC 1
Altera ALTCHIP_ID andi6510 0
LUT Questions Abdeljalil Bounaime 13
Simple question about a case statement Luis Gonzalez 1
VHDL project : 5 bit shift reg Michael 42
PS/2 module with LCD Luis Gonzalez 5
If or else if? Which is faster? techno-rogue 8
Vivado warning for RAM component Tudor Ioan 2
output comes after 1.2 sec delay after Power ON Naveedishtiaq Naveed 4
Error when trying to synthesize Tudor 5
sdram problem in vhdl quartus Vehbi Baycan 2