EmbDev.net

Forum: FPGA, VHDL & Verilog


Programmable logic


Subject Author Replies Last post
sticky FPGA development resources Andreas S. 15
Synthesis: Mix of sync and async assignments to register if else what when 5
Determining trace delay for input delay constraints Timing violation 13
Enhanced Tiger Single Board Computer Myron P. 3
Getting to the Root Cause of BGA Assembly Problems smartronics 1
How powerful is Verilog at using parameters to specify designs? Kevin S. 0
warning: Static variable initialization requires explicit lifetime in this context Kevin S. 2
Serializer verilog Atalin 9
Error in Loading Design NAZMUL HASAN 1
Input/feedback regarding desing using statemachine (VHDL) Lu F. 3
Gray counter verilog Gio97 6
What file suffix is usually used for the filename following a -o? Kevin S. 1
Is there anything beyond the Palnitkar book? Kevin S. 2
Right shift with VHDL Alex 7
Can anyone explain "cannot currently create a parameter of type" compilation error message? Kevin S. 0
In Verilog, why can't I compare my (genvar) with an integer value in my (for) loop? Kevin S. 3
Why can't I set a (genvar) outside the control section of a loop? Kevin S. 4
Can a function take a boolean argument? Kevin S. 5
Is it illegal to use an (enum) as a function input? Kevin S. 0
Having trouble understanding warnings and syntax errors in my Verilog. Kevin S. 2
How do I declare a packed array in Verilog? Kevin S. 3
Implement a VHDL program using with select for PAL James 2
Cannot get icarus to recognize enum or struct. Kevin S. 2
Free workshop materials: Integrating ARM Cortex M Processors into Xilinx FPGAs Alex W. 6
Double registering SparkyT 4
Step-by-Step Xilinx Vitis Getting Started Guides Alex W. 0
ISE synthesis warning changseon 1
Booth Multiplier Verilog code not working Prabhanshu 5
Converting table files (.tbl) to vector waveform files (.vwf) for simulation. Navi 0
matlab to vhdl malak 6
VHDL: Synchronizing an asynchronous interface without a clock Alex K. 2
Zedboard HDMI Pradeep T. 1
MIPS implementation Konstantinos D. 0
4Byte sequence to int Marthy .D 12
Run_length_encoding Leonardo 35
VHDL Useful Templates Alexander S. 41
VHDL Seven Segment Decoder Alexander S. 43
VHDL System Reset by PLL Locked Signal Alexander S. 7
VHDL Double and Single clocks designs compare Alexander S. 13
Dueprologic Cyclone iv fpga dev board Hareesh M. 6
VHDL Read and Read/Write Registers Alexander S. 0
VHDL Generic Multi Channel ADC SPI Controller Alexander S. 0
VHDL Generic ADC SPI Controller Alexander S. 8
VHDL error in project Fernando .S 5
vivado width mismatch error in synthesis Stefania M. 3
VHDL Generic Decoder Alexander S. 6
VHDL Generic Bus I/O MUX Alexander S. 6
VHDL Debouncer 4 clocks Alexander S. 19
Determining signal Nimesh S. 3
VHDL UART Design Alexander S. 3
VHDL Generic Spi Transmit by System Clock Speed Alexander S. 7
FPGA Embedded Design by Verilog Ankit D. 3