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Forum: FPGA, VHDL & Verilog


Programmable logic


Subject Author Replies Last post
sticky FPGA development resources Andreas S. 7
4 bit ALU variable name question Andrew M. 1
locked VHDL (GHDL): can't have multiple entities in file? Edmund 15
Servomotor. PWM and VHDL Soko Loko 12
Manual Clock Aldemaro G. 0
Comments on: Beitrag "Re: Erfahrung mit SPI Slave und Spartan 6 FPGA?" SparkyT 5
Vhdl time window Luca M. 15
VHDL output signal in hexadecimal instead of binary Guest 3
FIFO MEMORY VHDL Patryk S. 17
Duty and phase control clock divider Greg W. 2
cobverting 64 bit to 32 bit. slim_pga 6
Viscometer vhdl Emil Lagrange 2
Matrix Display Josip J. 2
force input in simulation wrong. fuck_modelsim 2
vhdl code to find max value of stream of unsigned 8 bit values Jeevan R. 2
decoder in vhdl dont work in simulation. ee_vhdl 5
Keeping Hierarchy in post-layout simulation using Microsemi designer Daveburton D. 1
Rising and falling edges Bob T. 1
BlocklyVHDL visual VHDL editor Hans 3
Generating SAIF file dayana42200 1
Testing I2C on cyclone 2 board Hareesh M. 12
Quartus II: How to disable most synthesis optimizations options Johannes 0
Verilog help MUHAMMAD FARHAN 1
Barrel Shifter Omar 7
fixed combo logic Bogdan 2
Problem with ultrasonic sensor, Luis Alfredo 1
UART RECEIVER Hareesh M. 7
method for modeling circuit Mohammad Mothermohammad 7
UART transmitter Hareesh M. 16
** Error: (vcom-66) Execution of vlib failed. Please check the error log for more details. Amalia 1
Scrolling a text on a 7-seg display Giorgia 3
Package for parametric design Ido 2
Procedure in VHDL testbench Bah 2
Lattice MachXO2 EFB library can't not found Robingao 1
VHDL multiplication for std_logic_vector Miguel 0
Datapath 8 bits VHDL Modelsim KleinBagel 3
Word Processing using verilog dayana42200 2
square root verilog Julia 5
Dont care in Array assignment HO Man Chan 1
Survey on FPGA-based Accelerators for CNNs Sparsh M. 0
constrain implementation Sophie Ttazeaee 5
Modelsim Vhdl library lpm not found. nehssen sock 10
A super basic question about behavioral modeling Chang L. 0
Interface DHT22 to FPGA Bùi Cường 6
FPGA/VHDL Channel on twitch Fpga_Guru 1
wired_and , wired_or VHDL Aldemaro G. 7
Verilog : postive Edge Trigger Saraswathy S. 2
12 Hour Clock problem PAUL W. 1
help in reading a large text file using verilog. Alangs Kannan 15
Weird warning for my design dayana42200 17
I don't understand this Aldemaro G. 5
ERROR - Design is empty yasoua 4