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Forum: FPGA, VHDL & Verilog


Programmable logic


Subject Author Replies Last post
sticky FPGA development resources Andreas S. 9
sine wave in vhdl Sheikh S. 5
N samples from an ADC Aron L. 3
clocking module in vivado? Flat B. 1
what kind of memory should i use? Flat B. 5
Write in a file with verilog XaBla 2
help writing testbench for uart mike 6
BITSLIP FUNCTION STATEMACHINE atif 1
How can I add the status of lights “red-yellow” in Verilog Michał W. 1
Reusing registers in VHDL FSM code Darian Reyes 3
Keypad saved shifting display in Verilog Cm Y. 0
register clear on read vhdl 3
how to open a ready project inside library work in modelsim ee_vhdl 2
PWM with 4-bits control in Verilog Cm Y. 13
ULX3S powerful ECP5 board for open source FPGA Goran M. 0
Project System Password Autielli Mako 1
Wifi audio hub Chaminda J. 8
Code VHDL/Verilog Spartan 3E - Solar Panel Freddy S. 2
ws2812 vhdl problem Flat B. 4
Variable clock with prescaler? Mohamed H. 2
How to connect an external FIFO to FPGA Charlie H. 1
fpga soartan 6 io pins are no longer working ahmeddarwish 0
Increase the frequency abdelhak taamouch 2
gpio pull-down demsp 2
$fwrite usage clarification Andrew M. 0
Problem with Writing a SDRAM Controller Mehdi 1
Altera Cyclone IV Internal Memory - ROM: 1-Port Problem Adrian H. 2
pass transistor Dong Wang 29
System Verilog alarm clock Andrew M. 1
Dueprologic Cyclone iv fpga dev board Hareesh M. 5
pass transistor logic monish 1
SPI slave design idea? Jack BK 25
TCS34725 Basys3 VHDL kimsinki 0
Modifying a PCA955 vhdl code Guest 2
How To Read A SD Card Adrian H. 6
FPGA Algorithms and Applications in the IoT, AI, and High-Performance Computing - Invitation to Edit Daniel N. 0
Sending and receiving somme data within FPGA Mafah M. 4
eye scan (eye diagram) kamal 1
Green/Red detector and button controlled car (BASYS3/VHDL) kilimci 1
VHDL - RTL design references George R. 2
how to do testbench nadirah 5
VGA 640x480 project Adrian H. 9
Neural Network on Xilinx Virtex 5 Electronics_hobbyist E. 9
4 bit ALU variable name question Andrew M. 1
locked VHDL (GHDL): can't have multiple entities in file? Edmund 15
Servomotor. PWM and VHDL Soko Loko 12
Manual Clock Aldemaro G. 0
Comments on: Beitrag "Re: Erfahrung mit SPI Slave und Spartan 6 FPGA?" SparkyT 5
Vhdl time window Luca M. 15
VHDL output signal in hexadecimal instead of binary Guest 3
FIFO MEMORY VHDL Patryk S. 17
Duty and phase control clock divider Greg W. 2