I have included a multi-module example from Intels site.
My 1st question is how do I know which inputs and outputs need to be
declared? In the example code intsig is not in the port list. Is this
because it is only used internal to the module, and if so no internal
ports need to be in the list?
My 2nd question is related to Xilinx Vivado IDE but maybe it applies to
most IDE's. If I create 3 files for the modules listed in the example
in my project is there any linker step like in C coding or will Vivado
automatically find them?
top_ver.v
module top_ver (q, p, r, out);
input q, p, r;
output out;
reg out, intsig;
bottom1 u1(.a(q), .b(p), .c(intsig));
bottom2 u2(.l(intsig), .m(r), .n(out));
endmodule
bottom1.v
module bottom1(a, b, c);
input a, b;
output c;
reg c;
always
begin
c<=a & b; end endmodule
bottom2.v
module bottom2(l, m, n);
input l, m;
output n;
reg n;
always
begin
n<=l | m; end endmodule
Kevin S. wrote: > is there any linker step like in C 1. Forget all you know about C. 2. Read the manual about the toolchain and the tools inside. 3. The toolchain is controlled by TCL scripts behind the GUI. > will Vivado automatically find them? As long as you have them in you project tree. > how do I know which inputs and outputs need to be declared? You need to declare those signals as inputs and outputs which *your design* needs to be inputs and outputs.
Thanks so much for the reply! I'm still fussy on what to declare thou. (intsig) is a output used internal to the module but it is not declared. reg out, intsig;
:
Edited by User
Kevin S. wrote: > (intsig) is a output used internal to the module It is not declared as output, its just a internal signal for interconnecting. > but it is not declared. 'intsig' and 'out' are declared to be a register in this line: input q, p, r; output out; reg out, intsig; As far as I can see there is no need for a register, as there is only combinatorial logic throughout the whole design. But I'm not the Verilog pro, it's way too implicit for me with a lot of "things which behave so because they behave so". Some call such implicit things simply to be a "rule of thumb": https://www.verilogpro.com/verilog-reg-verilog-wire-systemverilog-logic/ For me "rule of thumb" sounds not very different from "rule of dumb"... 😉
:
Edited by Moderator
Disclaimer: most of what I know about Verilog comes from Simon Monk: Programming FPGAs Getting Started with Verilog I also understand that Verilog has been revised a lot, and there may be things you can do, but shouldn't. The way I've learned it the most basic signal is a wire, and this must be driven constantly using an "assign" statement. a "reg" signal has a state, so it can be driven in an "always" block. If the "always" block doesn't drive it then it becomes a "latch", holding its current value. If all paths through the block write to the reg then it won't create a latch though. Incidentally regarding a "linker" it appears as if the IDE has a hidden fixed "make" process, so if you declare modules correctly the IDE figures out the build process by magic. Oh and a non-blocking assignment "<=" means a reg will take on the new value NEXT after the block has finished. Probably an oversimplification but important for synchronous blocks.
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