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Forum: FPGA, VHDL & Verilog Error when running modelsim


von Mart Bent (Guest)


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Hello,

for a school assignment I have to design a small ALU in vhdl which is 
able to run some basic instructions, this is made in quartus II web 
edition.

When I compile and analyze the file with quartus no syntax errors are 
found, but when running the model sim I get an syntax error.

I have already tried renaming the variables of the entity and re writing 
the code in different ways but I just cant get it to work.

This is the error displayed in the modelsim log:

# do ALU.do
  # ** Warning: (vlib-34) Library already exists at "work".
  #
  # Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 
2012
  # -- Compiling module ALU
  #
  # Top level modules:
  #   ALU
  # Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 
2012
  # -- Compiling module ALU_vlg_sample_tst
  # -- Compiling module ALU_vlg_check_tst
  # ** Error: ALU.vt(62): near ",": syntax error, unexpected ','
  # ** Error: c:/altera/13.0sp1/modelsim_ase/win32aloem/vlog failed.
  # Executing ONERROR command at macro ./ALU.do line 4

I have attached the vhdl file and the generated vt file.

Thanks and regards,

Mart

von Lothar M. (lkmiller) (Moderator)


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Mart Bent wrote:
> I have already tried
Trying is not really a useful or reliable way to get to a desired point.

Never ever do this:
1
use ieee.std_logic_arith.all;
2
use ieee.std_logic_unsigned.all;
3
use ieee.numeric_std.all;
Both math libs std_logic_xxx and numeric_std define some similar data 
types and some similar artihmetic operations with them. You will 
encounter some strange problems and weird behaviour now and then.
A hint: only use the numeric_std. It has and it can all you need.

I see some "tricks" due to that:
1
       tempoutput <=  std_logic_vector(ieee.numeric_std.unsigned(opcode(2 downto 0))) or tempoutput;


> # ** Error: ALU.vt(62): near ",": syntax error, unexpected ','
Where is line 62?

> When I compile and analyze the file with quartus no syntax errors are
> found, but when running the model sim I get an syntax error.
Strange: a Verilog testbench and a VHDL module. What the heck!
Do you have mixed language support with your Modelsim license?

von Homework_Service @ Nightshift (Guest)


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module ALU_vlg_check_tst (
  output,
  sampler_rx
);

input [7:0] output;
wire [7:0] output;
...

Problem:
You use output as name, but it is a reserved keyword in verilog.

Solution:
Rename your signals named "output".

Hint:
Replaceing all "output" in the file will NOT do the trick (-:

von Homework_Service @ Nightshift (Guest)


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Hint2:
Here is the list with the reserved keywords 
http://www.csit-sun.pub.ro/courses/Masterat/Materiale_Suplimentare/Xilinx%20Synthesis%20Technology/toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/verilog10.html 
just to prevent you from renaming from "output" to another reserved 
keyword.

von Homework_Service @ Nightshift (Guest)


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But indeed, very strange, the ALU.vt was generated by Altera Tools ans 
does not respect keywords.

Lothar M. wrote:
> Strange: a Verilog testbench and a VHDL module. What the heck!
> Do you have mixed language support with your Modelsim license?

Works with the free Modelsim Intel FPGA Starter Edition 2020.1

von Mart B (Guest)


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Homework_Service's solution worked! I renamed the output signal to a 
other name and the simulation worked fine. Thanks everyone for helping 
me out.

Regards,

Mart

von Homework_Service @ Nightshift (Guest)


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Thanks for the feedback, good luck!

Greetings,
gustl

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