Forum: FPGA, VHDL & Verilog FPGA development resources

von Andreas S. (andreas) (Admin) Flattr this

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The main difference is that CPLDs are smaller than FPGAs, i.e. you can fit a lot more logic inside a FPGA than inside a CPLD.

  • CPLDs: address decoders, bus interfaces, simple memory controllers, (video) signal generators
  • FPGAs: complex CPUs, high speed I/O, signal processing, encryption

VHDL or Verilog?

The difference is mainly in syntax, you can get the same synthesis result with both languages. VHDL is more verbose than Verilog (which can be an advantage or disadvantage, depending on how you look at it). In Europe VHDL is much more widely used than Verilog, in the US Verilog seems to be slightly more popular.

Basic rules for VHDL development

See http://embdev.net/articles/VHDL.

Chip vendors


  • also see the FPGA vendors’ websites
  • Digilent


  • TODO

IP Cores

  • Opencores – CPUs, USB, Ethernet, encryption, …

If you want to suggest any additions to this post, please reply below.

von Juha (Guest)

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I think this site would be helpfull. Here is some basic things and some 
more advanced.

von Shahul A. (Company: pantech solution) (shahulakthar)

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Here is a Source for learning FPGA and VHDL concepts


von René D. (Company: www.dossmatik.de) (dose)

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for verfication


a good simulator is the combination GHDL and GTKwave


I have written an introduction for this simulator

von Warren T. (doctorwkt)

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I found the book "Free Range VHDL" to be an excellent book about the 
language and also about best practices when writing VHDL code. Link:

Cheers, Warren

von FPGA4student.com (Guest)

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von peter (Guest)

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i programmed fbga with xp2 lattice chip to switch lvds from ipu and gpu. 
The screen resolution of 1440x900 and 1600x900 is good. but 1920x1200 
results are bad. I think the data and clk channel n and p output from 
the chip is not good. You let me ask how I write code to ensure that clk 
and data out are good

von Mark P. (mphil)

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I found these IP for Ethernet very useful:

For those who likes C++ this is very good to fast and easily create CPU 
/ RISC-V systems for FPGAs:

von MARC M. (magicianpe)

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Simple VHDL Editor with access to IP Core library:


SBA (Simple Bus Architecture):


Some Open IP Cores for SBA:


von Dmitry A. Senjakin (Guest)

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A lot of FPGA-based processor cores.
Project has some cores, C-to-assm and assm-to-binary compiller, debug 
system and kernel software.
Multiprocessor cores, multithread cores.

von Vipin K. (Company: Nazarbayev University) (vipinkmenon)

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I am creating a Youtube playlist for those who are interested to 
start/learn/try hardware-software codesign with Xilinx Zynq APSoC 
platform. There are already 40 Videos and hoping to add about 100 Videos 
from basic to advanced level. Basic background in Verilog and C 
programming are assumed. All source code are made available through git 



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