Forum: FPGA, VHDL & Verilog error (12007) top-level design entity "projet" is undefined

von Lpsyco L. (Company: Haha) (lpsyco)

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I use Quartus II web version 12.0 sp2 web edition to encode small 
program the order of TPs.
when I compile the file itself with "Analyze Current File", everything 
goes well without error.
But when I compile the whole project, I get this error:

error (12007) top-level design entity "project" is undefined

Thank you for helping me to solve this problem.

von user (Guest)

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you have to select the toplevel vhdl file, right click -> set as 

von mandakini (Guest)

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Iam using Quartus 12.1 web edition to compile a simple helloworld.v file 
and get the following error.Cannot find toplevel.v file.Please help.

Error (12007): Top-level design entity "helloworld" is undefined

von imd (Guest)

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it worked thank you

von bteddy (Guest)

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"Error: Top-level design entity "*NAME*" is undefined"

This is what I did to correct.
1) check paths for spaces, none allowed.
2) check entity name can not start with number.
3) Assignment - Settings - General - Top-Level Entity  - "..."
4) From bottom up. select next entity up. Apply - OK.
5) Processing - "Start Compilation"
6) When complete. Tools - "Netlist Viewers" - "RTL Viewer"
   Don't know if this step is necessary. It's what I did.
7) Repeat from step 3) moving up for each entity in list.
8) when finished, one last time with first (bottom/original)
   "Entity Name"
9)  Done

This created what was missing that was needed.
I worked for me hope it works for you.


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