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Forum: FPGA, VHDL & Verilog Flashing digits from 0 to 9


von Ber 2. (ber25)


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Hi , Can you help me to write the vhdl file for next delivery?

Design and implement a circuit that successively flashes digits from 0 
to 9 on the 7-segment display HEX0. Each digit should be displayed for 
about one second. Use a counter to determine the one-second interval. 
The counter should be incremented by the 50 MHz clock signal provided on 
the DE2 board (CLOCK_50 input signal, to be managed as a clock input 
coming from the external world). Do not derive any other clock signals 
in your design; make sure that all the flipflops in your circuit are 
clocked directly by the 50 MHz clock signal.

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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Ber 2. wrote:
> Can you help me to write the vhdl file for next delivery?
Show what you have, then maybe one will help you.
But I don't think anyone is going to do your homework completely...

von Ber 2. (ber25)


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Lothar M. wrote:
> Ber 2. wrote:
>> Can you help me to write the vhdl file for next delivery?
> Show what you have, then maybe one will help you.
> But I don't think anyone is going to do your homework completely...
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library ieee;
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use ieee.std_logic_1164.all;
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entity flashing_LIGHTS is
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port (  CLOCK_50, KEY0 : in std_logic;
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    HEX0 : out std_logic_vector(0 to 6));
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end flashing_LIGHTS;
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architecture semi_behavioral of flashing_LIGHTS is
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component counter_4bit is
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port(  
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               enable,clk,clear:in std_logic;
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    Q: buffer std_logic_vector(3 downto 0));
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end component;
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component segment_7_decoder is
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PORT (a :IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
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      B :OUT STD_LOGIC_VECTOR(0 TO 6));
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end component;
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signal count_enable, clock, reset : std_logic;
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signal count : std_logic_vector(3 downto 0);
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begin
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clock<=CLOCK_50;
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reset <= KEY0;
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clock_counter: process (clock, reset)
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variable count : integer range 0 to 49999999;
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begin
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if reset = '1' then
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count := 0;
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count_enable<='0';
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elsif clock'event and clock='1' then
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  if count = 49999999 then
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  count_enable<='1';
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  count:=0;
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  else
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  count := count+1;
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  count_enable<='0';
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  end if;
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end if;
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end process;
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counter: counter_4bit port map
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(count_enable, clock, reset or (count(3) and count(0)), count);
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RAPP: segment_7_decoder port map(count, HEX0);
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end semi_behavioral;

: Edited by Moderator
von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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Lothar M. wrote:
> Show what you have
Why not implementing the 4 bit counter simplay as a counter from 0 to 9 
in the flashing_LIGHTS entity?
1
library ieee;
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use ieee.std_logic_1164.all;
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entity flashing_LIGHTS is
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port (  CLOCK_50, KEY0 : in std_logic;
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        HEX0 : out std_logic_vector(0 to 6));
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end flashing_LIGHTS;
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architecture semi_behavioral of flashing_LIGHTS is
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signal count : integer range 0 to 9 := 0;
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signal countsec : integer range 0 to 49999999 := 0;
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begin
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clock<=CLOCK_50;
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reset <= KEY0;
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clock_counter: process (CLOCK_50, reset)
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begin
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if reset = '1' then
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  count_enable<='0';
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elsif clock'event and clock='1' then
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  if countsec = 49999999 then -- one second is gone
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    countsec <= 0;
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    if count<9 then -- each second: increment the digit counter
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      count <= count+1;
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    else
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      count <= 0;
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    end if;
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  else
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    countsec <= count+1;
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  end if;
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end if;
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end process;
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HEX0 <= "1111110" when count=0  else
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        "0110000" when count=1  else
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        ...
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        "1111111" when count=8  else
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        "1110011"; --  count=9
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end semi_behavioral;
If you must use those 2 components counter_4bit and segment_7_decoder, 
then you will have to rip out the corresponding lines of code and put 
them in their own entities...


BTW:
Have a look at the few lines above the reply edit box:
1
Reply
2
Rules — please read before posting
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    Post long source code as attachment, not in the text
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    ...
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Formatting options
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    [vhdl]VHDL code[/vhdl]
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So pls attach VHDL code as *.vhdl file or use the [vhdl] tokens further 
on.

: Edited by Moderator
von Farheen (Guest)


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1
module Lab_6 (SW,CLOCK_50,Qa,Qb,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5);
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input [1:0] SW;
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input CLOCK_50;
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output reg [25:0] Qa;
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output reg [7:0] Qb;
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output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5;
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always @ (posedge CLOCK_50)
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begin 
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if (!SW[0])
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Qa <= 0;
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else if (SW[1])
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Qa <= Qa + 1;
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else
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Qa <= Qa;
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if (&Qa)
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Qb <= Qb + 1;
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else
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Qb <= Qb;
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end
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decoder D0 (Qb[3:0],HEX0);
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decoder D1 (Qb[7:4],HEX1);
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assign HEX2 = 7'b1111111;
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assign HEX3 = 7'b1111111;
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assign HEX4 = 7'b1111111;
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assign HEX5 = 7'b1111111;
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endmodule 
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module decoder (in,disp);
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input [3:0] in;
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output reg [6:0] disp;
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always @ (*)
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case (in)
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4'h0 : disp = 7'b1000000;
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4'h1 : disp = 7'b1111001;
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4'h2 : disp = 7'b0100100;
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4'h3 : disp = 7'b0110000;
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4'h4 : disp = 7'b0011001;
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4'h5 : disp = 7'b0010010;
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4'h6 : disp = 7'b0000010;
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4'h7 : disp = 7'b1111000;
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4'h8 : disp = 7'b0000000;
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4'h9 : disp = 7'b0010000;
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4'hA : disp = 7'b0001000;
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4'hB : disp = 7'b0000011;
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4'hC : disp = 7'b1000110;
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4'hD : disp = 7'b0100001;
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4'hE : disp = 7'b0000110;
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4'hF : disp = 7'b0001110;
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endcase

: Edited by Moderator
von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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Farheen wrote:
1
 utput reg [25:0] Qa;
2
 output reg [7:0] Qb;
3
:
4
 always @ (posedge CLOCK_50)
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:
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 Qa <= Qa + 1;
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:
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 if (&Qa)
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 Qb <= Qb + 1;
This requirement is not satisfied:
Ber 2. wrote:
> Each digit should be displayed for about one second.
Because the 25 Bit counter a is counting only 2**25 = 33554432 cycles 
and therefore the display time is only 670ms per digit.

: Edited by Moderator

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