EmbDev.net

Forum: FPGA, VHDL & Verilog Flashing digits from 0 to 9


von Ber 2. (ber25)


Rate this post
useful
not useful
Hi , Can you help me to write the vhdl file for next delivery?

Design and implement a circuit that successively flashes digits from 0 
to 9 on the 7-segment display HEX0. Each digit should be displayed for 
about one second. Use a counter to determine the one-second interval. 
The counter should be incremented by the 50 MHz clock signal provided on 
the DE2 board (CLOCK_50 input signal, to be managed as a clock input 
coming from the external world). Do not derive any other clock signals 
in your design; make sure that all the flipflops in your circuit are 
clocked directly by the 50 MHz clock signal.

von Lothar M. (lkmiller) (Moderator)


Rate this post
useful
not useful
Ber 2. wrote:
> Can you help me to write the vhdl file for next delivery?
Show what you have, then maybe one will help you.
But I don't think anyone is going to do your homework completely...

von Ber 2. (ber25)


Rate this post
useful
not useful
Lothar M. wrote:
> Ber 2. wrote:
>> Can you help me to write the vhdl file for next delivery?
> Show what you have, then maybe one will help you.
> But I don't think anyone is going to do your homework completely...
1
library ieee;
2
use ieee.std_logic_1164.all;
3
4
entity flashing_LIGHTS is
5
port (  CLOCK_50, KEY0 : in std_logic;
6
    HEX0 : out std_logic_vector(0 to 6));
7
end flashing_LIGHTS;
8
9
architecture semi_behavioral of flashing_LIGHTS is
10
11
component counter_4bit is
12
port(  
13
               enable,clk,clear:in std_logic;
14
    Q: buffer std_logic_vector(3 downto 0));
15
end component;
16
17
component segment_7_decoder is
18
PORT (a :IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
19
      B :OUT STD_LOGIC_VECTOR(0 TO 6));
20
end component;
21
22
signal count_enable, clock, reset : std_logic;
23
signal count : std_logic_vector(3 downto 0);
24
25
begin
26
27
clock<=CLOCK_50;
28
reset <= KEY0;
29
30
clock_counter: process (clock, reset)
31
variable count : integer range 0 to 49999999;
32
begin
33
if reset = '1' then
34
count := 0;
35
count_enable<='0';
36
elsif clock'event and clock='1' then
37
  if count = 49999999 then
38
  count_enable<='1';
39
  count:=0;
40
  else
41
  count := count+1;
42
  count_enable<='0';
43
  end if;
44
end if;
45
end process;
46
47
counter: counter_4bit port map
48
(count_enable, clock, reset or (count(3) and count(0)), count);
49
50
RAPP: segment_7_decoder port map(count, HEX0);
51
end semi_behavioral;

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)


Rate this post
useful
not useful
Lothar M. wrote:
> Show what you have
Why not implementing the 4 bit counter simplay as a counter from 0 to 9 
in the flashing_LIGHTS entity?
1
library ieee;
2
use ieee.std_logic_1164.all;
3
4
entity flashing_LIGHTS is
5
port (  CLOCK_50, KEY0 : in std_logic;
6
        HEX0 : out std_logic_vector(0 to 6));
7
end flashing_LIGHTS;
8
9
architecture semi_behavioral of flashing_LIGHTS is
10
11
signal count : integer range 0 to 9 := 0;
12
signal countsec : integer range 0 to 49999999 := 0;
13
14
begin
15
16
clock<=CLOCK_50;
17
reset <= KEY0;
18
19
clock_counter: process (CLOCK_50, reset)
20
begin
21
if reset = '1' then
22
  count_enable<='0';
23
elsif clock'event and clock='1' then
24
  if countsec = 49999999 then -- one second is gone
25
    countsec <= 0;
26
    if count<9 then -- each second: increment the digit counter
27
      count <= count+1;
28
    else
29
      count <= 0;
30
    end if;
31
  else
32
    countsec <= count+1;
33
  end if;
34
end if;
35
end process;
36
37
HEX0 <= "1111110" when count=0  else
38
        "0110000" when count=1  else
39
        ...
40
        "1111111" when count=8  else
41
        "1110011"; --  count=9
42
43
end semi_behavioral;
If you must use those 2 components counter_4bit and segment_7_decoder, 
then you will have to rip out the corresponding lines of code and put 
them in their own entities...


BTW:
Have a look at the few lines above the reply edit box:
1
Reply
2
Rules — please read before posting
3
    Post long source code as attachment, not in the text
4
    ...
5
Formatting options
6
    ...
7
    [vhdl]VHDL code[/vhdl]
8
    ...
So pls attach VHDL code as *.vhdl file or use the [vhdl] tokens further 
on.

: Edited by Moderator
von Farheen (Guest)


Rate this post
useful
not useful
1
module Lab_6 (SW,CLOCK_50,Qa,Qb,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5);
2
input [1:0] SW;
3
input CLOCK_50;
4
output reg [25:0] Qa;
5
output reg [7:0] Qb;
6
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5;
7
8
always @ (posedge CLOCK_50)
9
begin 
10
if (!SW[0])
11
Qa <= 0;
12
else if (SW[1])
13
Qa <= Qa + 1;
14
else
15
Qa <= Qa;
16
17
if (&Qa)
18
Qb <= Qb + 1;
19
else
20
Qb <= Qb;
21
22
end
23
24
decoder D0 (Qb[3:0],HEX0);
25
decoder D1 (Qb[7:4],HEX1);
26
27
assign HEX2 = 7'b1111111;
28
assign HEX3 = 7'b1111111;
29
assign HEX4 = 7'b1111111;
30
assign HEX5 = 7'b1111111;
31
32
endmodule 
33
34
35
module decoder (in,disp);
36
input [3:0] in;
37
output reg [6:0] disp;
38
39
always @ (*)
40
case (in)
41
4'h0 : disp = 7'b1000000;
42
4'h1 : disp = 7'b1111001;
43
4'h2 : disp = 7'b0100100;
44
4'h3 : disp = 7'b0110000;
45
4'h4 : disp = 7'b0011001;
46
4'h5 : disp = 7'b0010010;
47
4'h6 : disp = 7'b0000010;
48
4'h7 : disp = 7'b1111000;
49
4'h8 : disp = 7'b0000000;
50
4'h9 : disp = 7'b0010000;
51
4'hA : disp = 7'b0001000;
52
4'hB : disp = 7'b0000011;
53
4'hC : disp = 7'b1000110;
54
4'hD : disp = 7'b0100001;
55
4'hE : disp = 7'b0000110;
56
4'hF : disp = 7'b0001110;
57
endcase

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)


Rate this post
useful
not useful
Farheen wrote:
1
 utput reg [25:0] Qa;
2
 output reg [7:0] Qb;
3
:
4
 always @ (posedge CLOCK_50)
5
:
6
 Qa <= Qa + 1;
7
:
8
 if (&Qa)
9
 Qb <= Qb + 1;
This requirement is not satisfied:
Ber 2. wrote:
> Each digit should be displayed for about one second.
Because the 25 Bit counter a is counting only 2**25 = 33554432 cycles 
and therefore the display time is only 670ms per digit.

: Edited by Moderator

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.