Forum: FPGA, VHDL & Verilog floating point result is wrong

von Onur (Guest)

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Hello friends, the result of floating point multiplication on hardware 
is wrong. Although it is correct in the simulation, it is wrong when I 
upload it on Cmod A7.

library IEEE;
use IEEE.numeric_std.ALL;
use work.float_pkg.all;

entity test_block is
    Port (
        data_in : in std_logic_vector (31 downto 0);
        data_out : out std_logic_vector (31 downto 0)
end test_block;

architecture Behavioral of test_block is
    constant adc_coef : real := 0.000000298023223876953125;
    data_out <= to_slv(to_float(signed(data_in))*adc_coef);
end Behavioral;

I am multiplying the hexadecimal number x"000727AC" (decimal 468908) by 
0.000000298023223876953125. The result should be 0x3e0f1970 (float 
0.139745) as a single precision floating point. It turns out right in 
the simulation.

However, when I upload it on the card, the integrated logic analyzer 
shows as 0x34a8f197 (float 0.000000314682182).

The result that is correct in the simulation is wrong on the hardware. I 
tried to multiply with different numbers, the result is the same wrong. 
Why such wrong results?

von Vancouver (Guest)

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You can't implement an FP multiplication in real hardware just by 
writing "*" as for integer. FP mult is much more complex and the 
synthesis tool does not generate a hardware for that automatically. 
Remember that you need to multiply the mantissas, add the exponents, 
normalize if required, handle special cases like NaN etc. You will have 
to instantiate an FP multiplier core explicitely.

Did you have a look into the logfiles? There should also be an 
approriate warning about that.

VHDL makes hardware design easy, but not that easy...

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