# Forum: FPGA, VHDL & Verilog Converting binary number to seven-segment-display

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My goal is to convert a binary input number to a std_logic_vector
signaling which segments to activate/deactivate on a
seven-segment-display.
'segments' is basically a vector, with each bit representing a segment a
through g, with the display being enumerated clockwise from the top (a)
to the upper left (f). The middle segment is g.

When I run this, I get an error at each if line, telling me that the
'then's are wrong and that I should properly use a 'generate' - which is
not really what I am trying to do.
Can someone tell me how to fix this?
 1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity BCDDecoder is 5 6 port ( 7 digit : in std_logic_vector(3 downto 0); 8 segments : out std_logic_vector(6 downto 0) 9 ); 10 end BCDDecoder; 11 12 architecture rtl of BCDDecoder is 13 14 begin 15 16 if digit = "0000" then 17 segments <= "1111110"; 18 end if; 19 20 if digit = "0001" then 21 segments <= "0110000"; 22 end if; 23 24 if digit = "0010" then 25 segments <= "1101101"; 26 end if; 27 28 if digit = "0011" then 29 segments <= "1111001"; 30 end if; 31 32 if digit = "0100" then 33 segments <= "0110011"; 34 end if; 35 36 if digit = "0101" then 37 segments <= "1011011"; 38 end if; 39 40 if digit = "0110" then 41 segments <= "0011111"; 42 end if; 43 44 if digit = "0111" then 45 segments <= "1110000"; 46 end if; 47 48 if digit = "1000" then 49 segments <= "1111111"; 50 end if; 51 52 if digit = "1001" then 53 segments <= "1110011"; 54 end if; 55 end architecture rtl;

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Eric J. wrote:
> When I run this, I get an error at each if line
You can use if-then only inside a process. As a concurrent statement use
when-else or with-select:
https://insights.sigasi.com/tech/signal-assignments-vhdl-withselect-whenelse-and-case/

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