Forum: FPGA, VHDL & Verilog Problem accessing SDRAM memory from VHDL code

von Mart Bent (Guest)

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Hello everyone,

I am currently working on a FPGA system where a VGA controller is feeded 
with pixel data using a section of the SDRAM memory of a Nios II/e 
system. This should give the ability to flush pixel data in C. I am 
however, stuck on one problem. Whenever I try to increase the memory 
address used for addressing in VHDL the memory_out data does not seem to 

The VHDL code should constantly loop through the memory and send the 
data of the pixels into the VGA controller.

The code is pretty big so I have attached it as a vhdl file.

This is the C code running on the Nios:
int main(void) {
u8* addr = MEMORY_BASE; //Starting point of the video buffer
  *addr = 255;
*(addr+1) = 0;
*(addr+2) = 0;
*(addr+3) = 255;
I have also attached a picture of the the screen looks like when using 
this setup.

As is visible in the picture, the pixels on the screen keep having the 
same pattern of the first 4 pixels that are set in the C code: white, 
black, black, white. I suspect that the memory is not properly adjusting 
to the change of the frame_buf_addr in the VHDL code.

Does anyone know any solutions to this problem? This is for my first 
VHDL course so my apologies for any uncertainties or mistakes!


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