EmbDev.net

Forum: FPGA, VHDL & Verilog Memory Address Register not outputing the input


Memory Address Register not outputing the input
von Mahmoud R. (mahmoud899)

Attached files:
Rate this post
• ▲ useful
▼ not useful 
I have a simple program. I am trying to input the counter output into a 
memory address register and output the data that is in the memory 
address register.

Memory Address Register Code:
1
library ieee;

2
use ieee.std_logic_1164.all;

3
4
entity mar is

5
port(

6
    mar_clk, mar_clr, mar_en : in std_logic;

7
    mar_datain : in std_logic_vector(3 downto 0);

8
    mar_dataout : out std_logic_vector(3 downto 0)

9
);

10
end entity;

11
12
architecture behavioral of mar is

13
begin

14
    process(mar_clk, mar_clr, mar_en, mar_datain)

15
        begin

16
        if(mar_clr = '1') then

17
            mar_dataout <= (others => '0');

18
        elsif(mar_clk'event and mar_clk = '1') then

19
            if(mar_en = '0') then

20
                mar_dataout <= mar_datain;

21
            end if;

22
        end if;

23
    end process;

24
end behavioral;


Buffer4 Code:
1
library ieee;

2
use ieee.std_logic_1164.all;

3
4
entity buffer4 is

5
port(

6
    buff4_en : in std_logic;

7
    datain : in std_logic_vector( 3 downto 0 );

8
    dataout : out std_logic_vector( 3 downto 0 )

9
);

10
end entity;

11
12
architecture behavioral of buffer4 is

13
begin

14
    process(buff4_en, datain)

15
    begin

16
        if(buff4_en = '1') then

17
            dataout <= datain;

18
        else

19
            dataout <= (others => 'Z');

20
        end if;

21
    end process;

22
end behavioral;


Program Counter Code:
1
library ieee;

2
use ieee.std_logic_1164.all;

3
use ieee.std_logic_unsigned.all;

4
5
entity pc is

6
    port(

7
        pc_ld, pc_en, pc_clk, pc_rst : in std_logic;

8
        pc_datain : in std_logic_vector(3 downto 0);

9
        pc_dataout : out std_logic_vector(3 downto 0)

10
    );

11
end entity;

12
13
architecture behave of pc is

14
    signal count : std_logic_vector(3 downto 0) := "0001";

15
    signal temp : integer;

16
begin

17
    process(pc_clk, pc_rst)

18
    begin

19
        if(pc_rst = '1') then

20
            count <= (others => '0');

21
        elsif(pc_clk'event and pc_clk = '1') then

22
            if(pc_ld = '1') then

23
                count <= pc_datain;

24
            elsif(pc_en = '1') then

25
                count <= count;

26
                temp <= conv_integer(count);

27
                if(temp = 16) then

28
                    count <= (others => '0');

29
                end if;

30
                count <= count + 1;

31
            end if;

32
        end if;

33
    end process;

34
    pc_dataout <= count;

35
end behave;


Test Code:
1
library ieee;

2
use ieee.std_logic_1164.all;

3
4
entity test is

5
end entity;

6
7
architecture behave of test is

8
9
component mar

10
    port(

11
        mar_clk, mar_clr, mar_en : in std_logic;

12
        mar_datain : in std_logic_vector( 3 downto 0 );

13
        mar_dataout : out std_logic_vector( 3 downto 0 )    

14
    );

15
end component;

16
17
component pc

18
    port(

19
        pc_ld, pc_en, pc_clk, pc_rst : in std_logic;

20
        pc_datain : in std_logic_vector(3 downto 0);

21
        pc_dataout : out std_logic_vector(3 downto 0)   

22
    );

23
end component;

24
25
component buffer4

26
    port(

27
        buff4_en : in std_logic;

28
        datain : in std_logic_vector( 3 downto 0 );

29
        dataout : out std_logic_vector( 3 downto 0 )    

30
    );

31
end component;

32
33
signal databus : std_logic_vector(7 downto 0);

34
signal addressbus : std_logic_vector(3 downto 0);

35
36
signal gclk : std_logic;

37
signal mar_clr, mar_en : std_logic;

38
signal pc_ld, pc_en, pc_rst : std_logic;

39
40
signal buff4_en : std_logic;

41
signal dataout : std_logic_vector(3 downto 0);

42
43
signal mar_datain, mar_dataout : std_logic_vector(3 downto 0);

44
signal pc_dataout : std_logic_vector(3 downto 0);

45
46
begin

47
    U1 : pc port map(pc_ld, pc_en, gclk, pc_rst, databus(3 downto 0), pc_dataout);

48
    U2 : buffer4 port map(buff4_en, pc_dataout, databus(3 downto 0));

49
    U3 : mar port map(gclk, mar_clr, mar_en, databus(3 downto 0), addressbus);

50
51
    stim_process : process

52
    begin

53
        gclk <= '0';

54
        wait for 10 ns;

55
        pc_ld <= '0';

56
        pc_en <= '1';

57
        pc_rst <= '0';

58
        buff4_en <= '1';

59
        mar_clr <= '0';

60
        mar_en <= '0';

61
        gclk <= '1';

62
        wait for 10 ns;

63
    

64
        gclk <= '0';

65
        wait for 10 ns;

66
    

67
        assert false report "Reached end of test. Start GTKWave";

68
        wait;

69
    end process;

70
end behave;


I have attached the simulation of the test.vhdl. The Memory Address 
Registers takes the input and doesn't output it on the address bus. How 
can I make the Memory Address Register output the data on the address 
bus?

  


  




  

    Report post Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
  







      

      



  

    Re: Memory Address Register not outputing the input
  


  

    

      von
      
        FPGA NOTFALLSEELSORGE (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

  Rate this post
  

  •
  
  ▲ useful 
  

  ▼ not useful 
  		
  

  


  

      
In your PC:

1
count <= count;

2
temp <= conv_integer(count);

3
if(temp = 16) then

4
    count <= (others => '0');

5
end if;

6
count <= count + 1;


The last assignment is executed in the process. So you have always
count <= count + 1.
And count must not be 16 because pc_dataout is only 4 Bits wide.

  


  




  

    Report post Edit Delete Quote selected text Reply Reply with quote
  







      

      



  

    Re: Memory Address Register not outputing the input
  


  

    

      von
      
        FPGA NOTFALLSEELSORGE (Guest)
      
      


      
    


    

      
    

    

    

      

      

      Attached files:


      

        
    

  
  


  

  Rate this post
  

  •
  
  ▲ useful 
  

  ▼ not useful 
  		
  

  


  

      
The test is a joke.

1. All signals don't have a default value. So they are uninitialized, as 
you can see in your waveform.

2. You only provide one single clock cycle on gclk.

3. Because of 1.:
- mar_en is never set to '1'
- pc_ld is never set to '1'
- mar_datain is never set.

4. The signals
dataout
mar_datain
mar_dataout
in test are never set.

  


  




  

    Report post Edit Delete Quote selected text Reply Reply with quote
  








    

    

       Watch this topic

      |
         Disable multi-page view

    

        


Please log in before posting. Registration is free and takes only a minute.



  Existing account

  


  
  

  
    

      

        
          
        
        
          
        
      

      

        
          
        
        
          
        
      

    


    
    
    





  Do you have a Google/GoogleMail account? No registration required!

  Log in with Google account
  





  No account? Register here.