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Forum: FPGA, VHDL & Verilog Memory Address Register not outputing the input


von Mahmoud R. (mahmoud899)


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I have a simple program. I am trying to input the counter output into a 
memory address register and output the data that is in the memory 
address register.

Memory Address Register Code:
1
library ieee;
2
use ieee.std_logic_1164.all;
3
4
entity mar is
5
port(
6
    mar_clk, mar_clr, mar_en : in std_logic;
7
    mar_datain : in std_logic_vector(3 downto 0);
8
    mar_dataout : out std_logic_vector(3 downto 0)
9
);
10
end entity;
11
12
architecture behavioral of mar is
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begin
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    process(mar_clk, mar_clr, mar_en, mar_datain)
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        begin
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        if(mar_clr = '1') then
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            mar_dataout <= (others => '0');
18
        elsif(mar_clk'event and mar_clk = '1') then
19
            if(mar_en = '0') then
20
                mar_dataout <= mar_datain;
21
            end if;
22
        end if;
23
    end process;
24
end behavioral;

Buffer4 Code:
1
library ieee;
2
use ieee.std_logic_1164.all;
3
4
entity buffer4 is
5
port(
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    buff4_en : in std_logic;
7
    datain : in std_logic_vector( 3 downto 0 );
8
    dataout : out std_logic_vector( 3 downto 0 )
9
);
10
end entity;
11
12
architecture behavioral of buffer4 is
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begin
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    process(buff4_en, datain)
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    begin
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        if(buff4_en = '1') then
17
            dataout <= datain;
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        else
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            dataout <= (others => 'Z');
20
        end if;
21
    end process;
22
end behavioral;

Program Counter Code:
1
library ieee;
2
use ieee.std_logic_1164.all;
3
use ieee.std_logic_unsigned.all;
4
5
entity pc is
6
    port(
7
        pc_ld, pc_en, pc_clk, pc_rst : in std_logic;
8
        pc_datain : in std_logic_vector(3 downto 0);
9
        pc_dataout : out std_logic_vector(3 downto 0)
10
    );
11
end entity;
12
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architecture behave of pc is
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    signal count : std_logic_vector(3 downto 0) := "0001";
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    signal temp : integer;
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begin
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    process(pc_clk, pc_rst)
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    begin
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        if(pc_rst = '1') then
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            count <= (others => '0');
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        elsif(pc_clk'event and pc_clk = '1') then
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            if(pc_ld = '1') then
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                count <= pc_datain;
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            elsif(pc_en = '1') then
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                count <= count;
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                temp <= conv_integer(count);
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                if(temp = 16) then
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                    count <= (others => '0');
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                end if;
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                count <= count + 1;
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            end if;
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        end if;
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    end process;
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    pc_dataout <= count;
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end behave;

Test Code:
1
library ieee;
2
use ieee.std_logic_1164.all;
3
4
entity test is
5
end entity;
6
7
architecture behave of test is
8
9
component mar
10
    port(
11
        mar_clk, mar_clr, mar_en : in std_logic;
12
        mar_datain : in std_logic_vector( 3 downto 0 );
13
        mar_dataout : out std_logic_vector( 3 downto 0 )    
14
    );
15
end component;
16
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component pc
18
    port(
19
        pc_ld, pc_en, pc_clk, pc_rst : in std_logic;
20
        pc_datain : in std_logic_vector(3 downto 0);
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        pc_dataout : out std_logic_vector(3 downto 0)   
22
    );
23
end component;
24
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component buffer4
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    port(
27
        buff4_en : in std_logic;
28
        datain : in std_logic_vector( 3 downto 0 );
29
        dataout : out std_logic_vector( 3 downto 0 )    
30
    );
31
end component;
32
33
signal databus : std_logic_vector(7 downto 0);
34
signal addressbus : std_logic_vector(3 downto 0);
35
36
signal gclk : std_logic;
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signal mar_clr, mar_en : std_logic;
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signal pc_ld, pc_en, pc_rst : std_logic;
39
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signal buff4_en : std_logic;
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signal dataout : std_logic_vector(3 downto 0);
42
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signal mar_datain, mar_dataout : std_logic_vector(3 downto 0);
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signal pc_dataout : std_logic_vector(3 downto 0);
45
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begin
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    U1 : pc port map(pc_ld, pc_en, gclk, pc_rst, databus(3 downto 0), pc_dataout);
48
    U2 : buffer4 port map(buff4_en, pc_dataout, databus(3 downto 0));
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    U3 : mar port map(gclk, mar_clr, mar_en, databus(3 downto 0), addressbus);
50
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    stim_process : process
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    begin
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        gclk <= '0';
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        wait for 10 ns;
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        pc_ld <= '0';
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        pc_en <= '1';
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        pc_rst <= '0';
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        buff4_en <= '1';
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        mar_clr <= '0';
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        mar_en <= '0';
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        gclk <= '1';
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        wait for 10 ns;
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        gclk <= '0';
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        wait for 10 ns;
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        assert false report "Reached end of test. Start GTKWave";
68
        wait;
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    end process;
70
end behave;

I have attached the simulation of the test.vhdl. The Memory Address 
Registers takes the input and doesn't output it on the address bus. How 
can I make the Memory Address Register output the data on the address 
bus?

von FPGA NOTFALLSEELSORGE (Guest)


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In your PC:
1
count <= count;
2
temp <= conv_integer(count);
3
if(temp = 16) then
4
    count <= (others => '0');
5
end if;
6
count <= count + 1;

The last assignment is executed in the process. So you have always
count <= count + 1.
And count must not be 16 because pc_dataout is only 4 Bits wide.

von FPGA NOTFALLSEELSORGE (Guest)


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The test is a joke.

1. All signals don't have a default value. So they are uninitialized, as 
you can see in your waveform.

2. You only provide one single clock cycle on gclk.

3. Because of 1.:
- mar_en is never set to '1'
- pc_ld is never set to '1'
- mar_datain is never set.

4. The signals
dataout
mar_datain
mar_dataout
in test are never set.

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