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Forum: FPGA, VHDL & Verilog johnson counter


von VhdlTest V. (Company: electronic srl) (vhdluser)


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someone can help me with this vhdl code for johnson counter. here is my 
implementation, I'm note sure about that. The correct image is the 
second one.


I have written this code in a first vhdl file, This is the Flip flop 
declaration, I will use it  as a component later :
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entity register_Johnson_entity is
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port (D : in std_logic_vector (2 downto 0); clock : in std_logic; reset: in std_logic; q: out std_logic_vector(2 downto 0));
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end register_Johnson;
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architecture reg_johnson of register_Johnson_entity is
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 flip_flop_async : process( clock, reset)
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 begin
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 if reset = '1' then 
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 q <= (others => "000")
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 else 
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 q<= D;
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 end if;
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 end process;
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 end architecture;

this is the other file that containt the main code, and where I use the 
component flip flop async:
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use ieee.std_logic_1164.all;
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entity counter_johnson is
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port (clock: in std_logic; tc: std_logic_vector(2 downto 0);
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end entity;
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architecture john of counter_johnson is
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 signal feedback : std_logic_vector(2 downto 0);
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 signal q : std_logic_vector (2 downto 0);
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 component register_Johnson_entity is
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  port (D : in std_logic_vector (2 downto 0); clock : in std_logic; reset: in std_logic; q: out std_logic_vector(2 downto 0));
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end register_Johnson;
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end component;
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-- registers update
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q(1)<=q(0);
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q(2)<=q(1);
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q(2)<= not q(0);
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-- the counter is cleared when tc =1
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reset_jonshon : process(q(2),q(1))
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 tc<=  q(2) and not q(1);
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 if tc == '1' then
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 -- reset operation
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 q(1)=(2)=q(0)= '0';
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 else tc == '0';
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 end process;
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-- port map operation
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port map (not feedback => D ;q(0) => D; q(1) => d );

: Edited by User
von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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VhdlTest V. wrote:
> This is the Flip flop declaration
Uhmmm...
This is a kind of some "dual-edge-flipflop". But only in simulation. In 
real life it is a latch. And only two kind of people are using latches: 
first those, who know them and their behavior very well. And second 
those who don't.

You belong to the second ones.

A hint: only simulation shows some kind of interest in the sensitivity 
list. The synthesizer don't. It only tells you, that the simulation 
doesn't math the synthesis result.
So look at your code as if there is no sensitivity list.

Having got that right look how others describe a flipflop in VHDL. A 
hint here: it has something to do with 'event or rising_edge() or 
falling_edge(). The two functions are built on the' event.

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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VhdlTest V. wrote:
1
-- the counter is cleared when tc =1
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reset_jonshon : process(q(2),q(1)) // tc is missing here, will result in weird behaviour
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 tc<=  q(2) and not q(1); // assigning a bit to a vector will not work
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 if tc == '1' then   // comparisons look much different, we do not 'C'
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 -- reset operation
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 q(1)=(2)=q(0)= '0'; // assignments do look much different
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 else tc == '0';     // assignments do look much different
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 end process;
Such nasty syntax errors you have throughout the whole code starting at 
the very first line! Just hand your scribblescrabble over to the syntax 
check to get rid of 90% of the errors. And then post it to anyone 
around the world.

> -- reset operation
>  q(1)=(2)=q(0)= '0';
What means the lonely (2) here? Why do you expect such a kind of "queued 
up assignement" is working in VHDL? And why not simply writing q <= 
"000"?

Keep your eyes on a clean and correct sensitivity list or use VHDL-2008 
and the keyword "all" instead of listing single signals.

And at all: i don't see no need for a "reset" in your picture...

My VHDL code for the pictures above would look like this:
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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entity counter is
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  port (clock: IN  std_logic;
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        tc:    OUT std_logic_vector(2 downto 0));
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end counter;
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architecture john of counter is
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  signal c : std_logic_vector(2 downto 0) := "000";
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begin  
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  process begin
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    wait until rising_edge (clock);
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    if (c /= "100") then  c <= c(1) & c(0) & not c(2);    
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    else                  c <= "000";
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    end if;
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  end process;
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  tc <= c;
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end john;
Or a little bit shorter:
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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entity counter is
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  port (clock: IN  std_logic;
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        tc:    OUT std_logic_vector(2 downto 0));
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end counter;
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architecture john of counter is
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  signal c : std_logic_vector(2 downto 0) := "000";
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begin  
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  c <= c(1) & c(0) & not c(2) when rising_edge(clock);
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  tc <= c;
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end john;
And both of them result in the attached waveform.

: Edited by Moderator

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