Forum: FPGA, VHDL & Verilog connecting components together

von Durko Rurko (Guest)

Rate this post
not useful
Hi guys. I am student at high school interested in VHDL programming. I 
have three components and I would like to connect them to one component 
this way. First component has some input. Output of this component is 
input to the second component and outpu of the second component is input 
of third component and this component produces output. Could anyone 
please help me with this ? If so, please contact me on the mail I have 
attached. I would really appreciate some help. Thank you.

Email Addresss: durko208@gmail.com

von Lothar M. (Company: Titel) (lkmiller) (Moderator)

Rate this post
not useful
Durko Rurko wrote:
> If so, please contact me on the mail
This is not the way a forum works, you know?

Additionally I don't think you'll have too much luck in finding someone 
to do your homework.

So, let's handle it the way we handle it: you start with something and 
when you encounter specific problems, then you ask for help.


Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.