# Forum: FPGA, VHDL & Verilog Modelsim Altera verilog Error state emory exceed but i'm pretty sure there's plenty of space left

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First, i gotta say i'm grateful that you take your time for this So i'm
attempting a Huffman coding simulation from a list of symbol's character
frequencies from hex file. The result should display all the encoding
binary of input then write it to the appointed hex file. Thing went
smoothly for small number like 12 variable (12 numeric values of the
amount of time that symbol appear aka frequencies). but when i amp that
number up, say 50 (which i have redeclare in the input file), i
encounter an simulation error. (i'm using the 32 bit version of modelsim
altera, some suggest that i may run out of memory, but i'm pretty sure
i'm far from reaching that)

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** Fatal: (vsim-4) ****** Memory allocation failure. *****

Attempting to allocate 436207632 bytes

Time: 0 ps Iteration: 0 Instance: /testbench/dut/gen[26]/S1 File:
C:/Users/PC/Desktop/huffman-coding-master/HuffmanEncodingVerilog-master/
design

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i change the amount of input by change the value of parameter
total symbols = log2(TOTAL_SYMBOLS)) and maxhight (assume max hight of
tree). for instance symbols = 12, addr_width = 4, maxhight = 13 worked,
but symbols = 50, addr_width = 6, maxhight = 51 don't. i think that the
problem may lie in my testbench but i don't know where.

my full code is upload in a text file here, feel free to check it out.
and again, i'm really appreciate your help

https://drive.google.com/file/d/17-_1N-IQvUFdpbAvroTTgc5hC8GRmXDz/view?usp=sharing

: Edited by User

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