Static elaboration of top level VHDL design unit in library work failed. why could this happen? I created a testbench and vhdl code for command framing. through testbench passing input to vhdl. but i get the error like this
abith itty jacob wrote: > but i get the error like this What part of the toolchain is reporting that error? > why could this happen? There may be a problem within the unknown source code. You know its fairly tricky for a medic to find out whats wrong, when you only say "It hurts!" without adding more detaild information...
: Edited by Moderator
abith itty jacob wrote: > why could this happen? see manual of your toolchain
This might be as simple as a syntax error.