EmbDev.net

Forum: FPGA, VHDL & Verilog Counter with overflow signal at 1001


Counter with overflow signal at 1001
von Eric J. (coderic)

Rate this post
• ▲ useful
▼ not useful 
I am trying to make a counter that increases by one on every rising edge 
if enable = 1. Additionally, if reset = 1 on a rising edge, the counter 
should be reset. If the counter's current state is 9 (1001), overflow 
should be one.

1
library ieee;

2
use ieee.std_logic_1164.all;

3
use ieee.numeric_std.all;

4
5
entity BCDCounter is

6
7
port (

8
    clk : in std_logic;

9
    reset : in std_logic;

10
    count : out std_logic_vector(3 downto 0);

11
    enable : in std_logic;

12
    overflow : out std_logic

13
);

14
end BCDCounter;

15
16
architecture rtl of BCDCounter is

17
18
signal countr : unsigned(3 downto 0);

19
20
begin

21
    process(clk)

22
    begin

23
        if(rising_edge(clk)) then

24
            if enable = '1' then

25
                countr <= countr + 1;

26
                if std_logic_vector(countr) = "1001" then

27
                    countr <= (others => '0');

28
                end if;

29
            end if;

30
            if reset = '1' then

31
                countr <= (others => '0');

32
            end if;

33
        end if;

34
        if std_logic_vector(countr) = "1001" then

35
            overflow <= '1';

36
        else

37
            overflow <= '0';

38
        end if;

39
    end process;

40
    count <= std_logic_vector(countr);

41
end architecture rtl;


Upon running this code, I get a delayed overflow output on the switch 
from 9 to 10, and I have no idea why.

1
ENABLED  5 -> 0101 OVERFLOW 0 OK.

2
ENABLED  6 -> 0110 OVERFLOW 0 OK.

3
ENABLED  7 -> 0111 OVERFLOW 0 OK.

4
ENABLED  8 -> 1000 OVERFLOW 0 OK.

5
ENABLED  9 -> 1001 OVERFLOW 0 FALSE!

6
ENABLED  0 -> 0000 OVERFLOW 1 FALSE!

7
RESET to ENABLED  0 -> 0000 OVERFLOW 0 OK.

8
DISABLED 0 -> 0000 OVERFLOW 0 OK.

9
ENABLED  1 -> 0001 OVERFLOW 0 OK.

10
DISABLED 1 -> 0001 OVERFLOW 0 OK.


  


  




  

    Report post Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
  







      

      



  

    Re: Counter with overflow signal at 1001
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

  Rate this post
  

  •
  
  ▲ useful 
  

  ▼ not useful 
  		
  

  


  

      
Eric J. wrote:
> I have no idea why.
Congratulations, you found the thing called "latency". This is due to 
the values you are preparing in a synchronous process will happen "later 
on" at the very next active clock edge.

So lets play "synthesizer": you enter the process with number 9 and find 
that the overflow flag must be set.
Additionally in the very same process you find that 9 is enough and set 
0 as the next value.
And of course now the overflow flag will be active together with the 
counters value 0.

Have a look at the simulations waveform and think about what you see and 
I wrote. Sooner or later you will get the trick.

  


  




  

    Report post Edit Delete Quote selected text Reply Reply with quote
  








    

    

       Watch this topic

      |
         Disable multi-page view

    

        


Please log in before posting. Registration is free and takes only a minute.



  Existing account

  


  
  

  
    

      

        
          
        
        
          
        
      

      

        
          
        
        
          
        
      

    


    
    
    





  Do you have a Google/GoogleMail account? No registration required!

  Log in with Google account
  





  No account? Register here.