Counter with overflow signal at 1001

Eric J. (coderic) OP 2022-03-11 19:51 #7001144

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I am trying to make a counter that increases by one on every rising edge 
if enable = 1. Additionally, if reset = 1 on a rising edge, the counter 
should be reset. If the counter's current state is 9 (1001), overflow 
should be one.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BCDCounter is
    clk : in std_logic;
    reset : in std_logic;
    count : out std_logic_vector(3 downto 0);
    enable : in std_logic;
    overflow : out std_logic
end BCDCounter;
architecture rtl of BCDCounter is
signal countr : unsigned(3 downto 0);
    process(clk)
    begin
        if(rising_edge(clk)) then
            if enable = '1' then
                countr <= countr + 1;
                if std_logic_vector(countr) = "1001" then
                    countr <= (others => '0');
                end if;
            end if;
            if reset = '1' then
                countr <= (others => '0');
            end if;
        end if;
        if std_logic_vector(countr) = "1001" then
            overflow <= '1';
        else
            overflow <= '0';
        end if;
    end process;
    count <= std_logic_vector(countr);
end architecture rtl;


Upon running this code, I get a delayed overflow output on the switch 
from 9 to 10, and I have no idea why.

ENABLED  5 -> 0101 OVERFLOW 0 OK.
ENABLED  6 -> 0110 OVERFLOW 0 OK.
ENABLED  7 -> 0111 OVERFLOW 0 OK.
ENABLED  8 -> 1000 OVERFLOW 0 OK.
ENABLED  9 -> 1001 OVERFLOW 0 FALSE!
ENABLED  0 -> 0000 OVERFLOW 1 FALSE!
RESET to ENABLED  0 -> 0000 OVERFLOW 0 OK.
DISABLED 0 -> 0000 OVERFLOW 0 OK.
ENABLED  1 -> 0001 OVERFLOW 0 OK.
DISABLED 1 -> 0001 OVERFLOW 0 OK.

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Lothar M. (lkmiller) Moderator (Company: Titel) 2022-03-13 17:48 #7002632

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Eric J. wrote:
> I have no idea why.
Congratulations, you found the thing called "latency". This is due to 
the values you are preparing in a synchronous process will happen "later 
on" at the very next active clock edge.

So lets play "synthesizer": you enter the process with number 9 and find 
that the overflow flag must be set.
Additionally in the very same process you find that 9 is enough and set 
0 as the next value.
And of course now the overflow flag will be active together with the 
counters value 0.

Have a look at the simulations waveform and think about what you see and 
I wrote. Sooner or later you will get the trick.

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