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Forum: FPGA, VHDL & Verilog Counter with overflow signal at 1001


von Eric J. (coderic)


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I am trying to make a counter that increases by one on every rising edge 
if enable = 1. Additionally, if reset = 1 on a rising edge, the counter 
should be reset. If the counter's current state is 9 (1001), overflow 
should be one.
1
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity BCDCounter is
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port (
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    clk : in std_logic;
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    reset : in std_logic;
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    count : out std_logic_vector(3 downto 0);
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    enable : in std_logic;
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    overflow : out std_logic
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);
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end BCDCounter;
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architecture rtl of BCDCounter is
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signal countr : unsigned(3 downto 0);
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begin
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    process(clk)
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    begin
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        if(rising_edge(clk)) then
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            if enable = '1' then
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                countr <= countr + 1;
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                if std_logic_vector(countr) = "1001" then
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                    countr <= (others => '0');
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                end if;
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            end if;
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            if reset = '1' then
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                countr <= (others => '0');
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            end if;
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        end if;
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        if std_logic_vector(countr) = "1001" then
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            overflow <= '1';
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        else
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            overflow <= '0';
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        end if;
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    end process;
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    count <= std_logic_vector(countr);
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end architecture rtl;

Upon running this code, I get a delayed overflow output on the switch 
from 9 to 10, and I have no idea why.
1
ENABLED  5 -> 0101 OVERFLOW 0 OK.
2
ENABLED  6 -> 0110 OVERFLOW 0 OK.
3
ENABLED  7 -> 0111 OVERFLOW 0 OK.
4
ENABLED  8 -> 1000 OVERFLOW 0 OK.
5
ENABLED  9 -> 1001 OVERFLOW 0 FALSE!
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ENABLED  0 -> 0000 OVERFLOW 1 FALSE!
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RESET to ENABLED  0 -> 0000 OVERFLOW 0 OK.
8
DISABLED 0 -> 0000 OVERFLOW 0 OK.
9
ENABLED  1 -> 0001 OVERFLOW 0 OK.
10
DISABLED 1 -> 0001 OVERFLOW 0 OK.

von Lothar M. (lkmiller) (Moderator)


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Eric J. wrote:
> I have no idea why.
Congratulations, you found the thing called "latency". This is due to 
the values you are preparing in a synchronous process will happen "later 
on" at the very next active clock edge.

So lets play "synthesizer": you enter the process with number 9 and find 
that the overflow flag must be set.
Additionally in the very same process you find that 9 is enough and set 
0 as the next value.
And of course now the overflow flag will be active together with the 
counters value 0.

Have a look at the simulations waveform and think about what you see and 
I wrote. Sooner or later you will get the trick.

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