Assignment of the Ports / Signals (Lattice Diamond)

Pascal Guest 2022-09-16 22:26 #7194301

Hello all

I use the IDE Diamond from Lattice.
VHDL beginner (!) ...but there is already a question to be asked.
Assignment of the Ports / Signals

As far as I can see, I only define in the VHDL code if a port is an 
input / output. But when I synthesize the design, all inputs are 
signaled as clock signals, which is not correct. The should be assigned 
as normal inputs
Hope my problem is a bit more understandable with the pictures :-)

Question: How can I make TX-uC and RX1-RX8 normal inputs?

Many thanks for your help (in advance)
Pascal

Attached files:

Entity.jpg (220 KB)
Spreadsheet_view.jpg (230 KB)

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Lothar M. (lkmiller) Moderator (Company: Titel) 2022-09-18 23:03 #7196326

Pascal wrote:
> all inputs are signaled as clock signals, which is not correct.
Maybe you don't want or expect them to be clock inputs, but your 
code is written in a way that the synthesizer recognizes all those input 
signals as clocks.

As often the problem is not in the supplied snippet of code, it is 
buried somewhere else in the code itself. So simply attach the 
questionable VHDL file.

Pascal wrote:
> Hope my problem is a bit more understandable with the pictures :-)
Never ever post any source code as a picture. Its very difficult to edit 
source code delivered as a picture. Or to cut and paste a snippet of 
code out of such a picture. Got the trick?

BTW1: why tose old fashioned std_logic_arith package out of the last 
millenium. Use the numeric_std instead.

BTW2: why TX1..TX8 when VHDL allows you to define a vector TX(1 to 8)?

BTW3: why TX1..TX8 when usually a hardware designer would use TX7..TX0 
or better TX(7 downto 0) for an 8-bit bus?

BTW4: you could ask the question in German by using the German part of 
the forum: https://www.mikrocontroller.net/forum/fpga-vhdl-cpld

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