Engin wrote:
> How can I write 14-bit incrementer VHDL code?
Somehow like this:

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entity incr is

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  port( inval  : in  std_logic_vector(13 downto 0);

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        outval : out std_logic_vector(13 downto 0));

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end entity;

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architecture rtl of incr is

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begin

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  outval <= inval + 1;

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end architecture;

Is that similar to what you understand by "incrementer"? If your 
expectations are different: what is different?

> Can you help me?
All in all: we will help you with your homework, no problem. But you 
must start with something. Just whining "please give me the code" will 
not lead to a result.

> I'm new at this job
Everybody was. Exercising and learning is the way to knowledge.