> if(res_in = '1' or Q4=1) then
You will get strange effects with this here because Q4 is a variabel,
and you can't put variables in the sensitivity list. But for
recalculating the process a signal in the sensitivity list *must
But at a closer look the whole sensitiviy list looks inconsistet and
therfore the simulation must be wrong.
One of the actual problems is: you do some weird things with clocks.
elsif(rising_edge(clk) and enb='1')
if(count_2=1 and rising_edge(tra))
To keep things short: "tra" for sure is not a clock!!!
A beginners design has only 1 clock: the one that is coming from the
quartz oscillator outside the FPGA. Only on this clock a 'event or a
risong_edge() or a falling_edge() has to be used.