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von daniel (Guest)


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Hello everyone, my English is not the best I would love patience.

I wrote a counter code designed to schedule the transfer of information 
from an array to a single output signal.

The problem is that it bounces the value of control j from zero to a 
maximum of one time.

I would love to know what the problem is, the goal is to split a vector 
of 24 into 3 vectors of 8 when count_2 = 1.

If I do not use the tra tra increase, and if I do it does not respond.
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process(clk,res_in)
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variable Q1 : integer range 0 to 2000:=0;
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variable Q2 : integer range 0 to 8:=0;
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variable Q3,Q4 : integer range 0 to 8:=0;
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begin
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if(res_in = '1' or Q4=1) then 
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    Q1:=0;
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    Q2:=0;
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    Q3:=0;
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    Q4:=0;
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            elsif(rising_edge(clk) and enb='1') then 
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            Q1:=Q1+1;
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                if(Q1=2000) then 
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                Q1:=0;
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                tra<=not(tra);
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                Q2:=Q2+1;
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                    if(Q2=8) then 
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                    Q2:=0;
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                    Q3:=Q3+1;
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                        if(Q3=8) then 
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                        Q3:=0;
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                        Q4:=Q4+1;
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                            if(Q4=8) then 
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                            Q4:=0;
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                            end if;
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                        end if;
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                    end if;
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               end if;
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         end if;   
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         if(count_2=1 and rising_edge(tra)) then 
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         if(j<7) then
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            Dataout(0)<=Data(j)(7 downto 0);
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            Dataout(1)<=Data(j)(15 downto 8);
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            Dataout(2)<=Data(j)(23 downto 16);
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            j<=j+1;
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          end if;
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         end if;
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count_1<=Q1;count_2<=Q2;count_3<=Q3;count_4<=Q4;
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end process;

von Lothar M. (lkmiller) (Moderator)


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daniel wrote:
> if(res_in = '1' or Q4=1) then
Ouch...
You will get strange effects with this here because Q4 is a variabel, 
and you can't put variables in the sensitivity list. But for 
recalculating the process a signal in the sensitivity list *must 
change*.

But at a closer look the whole sensitiviy list looks inconsistet and 
therfore the simulation must be wrong.

One of the actual problems is: you do some weird things with clocks.
1
:
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    elsif(rising_edge(clk) and enb='1') 
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:
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         if(count_2=1 and rising_edge(tra))
To keep things short: "tra" for sure is not a clock!!!

A beginners design has only 1 clock: the one that is coming from the 
quartz oscillator outside the FPGA. Only on this clock a 'event or a 
risong_edge() or a falling_edge() has to be used.

von daniel (Guest)


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That's fine, thank you very much I got along

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