EmbDev.net

Forum: FPGA, VHDL & Verilog 4bit counter with load test bench fail


von Christos Goulas (Guest)


Rate this post
useful
not useful
mux2to1:

library ieee;
use ieee.std_logic_1164.all;

entity mux2to1 is
  port(in1, in2, sel: in std_logic;
     output: out std_logic);
end entity;

architecture bahavioral of mux2to1 is
  begin
    process(in1, in2, sel)
      begin
        case sel is
          when '0' => output <= in1;
          when others => output <= in2;
        end case;
    end process;
end architecture;

d flip flop:

library ieee;
use ieee.std_logic_1164.all;

entity dff is
  port(d, clock, reset: in std_logic;
     q: out std_logic);
end entity;

architecture behavioral of dff is
  begin
    process(clock, reset)
      begin
        if rising_edge(clock) then
          if reset = '1' then
            q <= '0';
          else
            q <= d;
          end if;
        end if;
    end process;
end architecture;

counter:

library ieee;
use ieee.std_logic_1164.all;

entity counter is
  port(clock, reset, load, enable: in std_logic;
     d: in std_logic_vector(3 downto 0);
     a: out std_logic_vector(3 downto 0);
     carry: out std_logic);
end entity;

architecture structural of counter is
  component mux2to1
    port(in1, in2, sel: in std_logic;
         output: out std_logic);
  end component;

  component dff
    port(d, clock, reset: in std_logic;
         q: out std_logic);
  end component;

  signal xor_out, and_out, q_out, mux_out: std_logic_vector(3 downto 0);

  begin
    block00: mux2to1 port map(in1 => xor_out(0), in2 => d(0), sel => 
load, output => mux_out(0));
    block01: mux2to1 port map(in1 => xor_out(1), in2 => d(1), sel => 
load, output => mux_out(1));
    block02: mux2to1 port map(in1 => xor_out(2), in2 => d(2), sel => 
load, output => mux_out(2));
    block03: mux2to1 port map(in1 => xor_out(3), in2 => d(3), sel => 
load, output => mux_out(3));
    block04: dff port map (d => mux_out(0), clock => clock, reset => 
reset, Q => Q_out(0));
    block05: dff port map (d => mux_out(1), clock => clock, reset => 
reset, Q => Q_out(1));
    block06: dff port map (d => mux_out(2), clock => clock, reset => 
reset, Q => Q_out(2));
    block07: dff port map (d => mux_out(3), clock => clock, reset => 
reset, Q => Q_out(3));
    xor_out(0) <= q_out(0) xor enable;
    xor_out(1) <= q_out(1) xor and_out(0);
    xor_out(2) <= q_out(2) xor and_out(1);
    xor_out(3) <= q_out(3) xor and_out(2);
    and_out(0) <= enable and q_out(0);
    and_out(1) <= and_out(0) and q_out(1);
    and_out(2) <= and_out(1) and q_out(2);
    and_out(3) <= and_out(2) and q_out(3);
    carry <= and_out(3);
    a <= q_out;

end architecture;


Above is the code for the counter. What I want is to implement a 
testbench. Below is the testbench that I have written. But the testbench 
is not working properly. The clock, reset, enable and load take values 
properly but the d is undefined. How can I do it work?

testbench

library ieee;
use ieee.std_logic_1164.all;

entity counter_tb is
end entity;

architecture counter_tb_arch of counter_tb is
  component counter
    port(clock, reset, load, enable: in std_logic;
        d: in std_logic_vector(3 downto 0);
        a: out std_logic_vector(3 downto 0);
        carry: out std_logic);
  end component;

  signal clock_tb, reset_tb, load_tb, enable_tb: std_logic;
  signal d_tb: std_logic_vector(3 downto 0);
  signal a_tb: std_logic_vector(3 downto 0);
  signal carry_tb: std_logic;

  begin

    dut: counter port map(clock => clock_tb,
                reset => reset_tb,
                load => load_tb,
                enable => enable_tb,
                d => d_tb,
                a => a_tb,
                carry => carry_tb);

    reset_stim: process
      begin
        reset_tb <= '1'; wait for 20 ns;
        reset_tb <= '0'; wait;
    end process;

    clock_stim: process
      begin
        clock_tb <= '0'; wait for 20 ns;
        clock_tb <= '1'; wait for 20 ns;
    end process;

    enable_stim: process
      begin
        enable_tb <= '0'; wait for 50 ns;
        enable_tb <= '1'; wait;
    end process;

    load_stim: process
      begin
        load_tb <= '0'; wait;
    end process;


end architecture;

von Achim S. (Guest)


Rate this post
useful
not useful
Christos Goulas wrote:
> The clock, reset, enable and load take values
> properly but the d is undefined.

you have processes, that assign defined values to clock_tb, reset_tb, 
enable_tb and load_tb. But you do not assign anything to d_tb, which is 
an input of your counter.

Christos Goulas wrote:
> How can I do it work?

assign a defined signal to d_tb.

von Christos Goulas (Guest)


Rate this post
useful
not useful
Thanks for your response. Can you give me an example in order to test 
it.

von Achim S. (Guest)


Rate this post
useful
not useful
Christos Goulas wrote:
> Can you give me an example in order to test it.

are you serious?

well, maybe you try d_tb <= "1010";

von FPGA NOTFALLSEELSORGE (Guest)


Rate this post
useful
not useful
This will not solve his problems as there are several.

von Achim S. (Guest)


Rate this post
useful
not useful
it will solve, what he mentioned as problem:

Christos Goulas wrote:
> but the d is undefined.

maybe he recognizes the next problem in the next step.

von Christos Goulas (Guest)


Rate this post
useful
not useful
My updated testbench is below. I initialize the d_tb and when the 
load_tb = 0 the counter starts from 0. When load_tb = 1 I made it jump 
to 0101 and counts from there. How can I make it jump again into a new 
value. I put a new value to d_tb as you can see in load_stim process but 
the counter does not jump to the new value, rather continues from the 
last value. Thanks for responses and I am new to hdl programming, trying 
to understanding by myself, as I came from a programmer background

library ieee;
use ieee.std_logic_1164.all;

entity counter_tb is
end entity;

architecture counter_tb_arch of counter_tb is
  component counter
    port(clock, reset, load, enable: in std_logic;
        d: in std_logic_vector(3 downto 0);
        a: out std_logic_vector(3 downto 0);
        carry: out std_logic);
  end component;

  signal clock_tb, reset_tb, load_tb, enable_tb: std_logic;
  signal d_tb: std_logic_vector(3 downto 0) := "0000";
  signal a_tb: std_logic_vector(3 downto 0);
  signal carry_tb: std_logic;

  begin

    dut: counter port map(clock => clock_tb,
                reset => reset_tb,
                load => load_tb,
                enable => enable_tb,
                d => d_tb,
                a => a_tb,
                carry => carry_tb);

    reset_stim: process
      begin
        reset_tb <= '1'; wait for 21 ns;
        reset_tb <= '0'; wait;
    end process;

    clock_stim: process
      begin
        clock_tb <= '0'; wait for 20 ns;
        clock_tb <= '1'; wait for 20 ns;
    end process;

    enable_stim: process
      begin
        enable_tb <= '0'; wait for 50 ns;
        enable_tb <= '1'; wait;
    end process;

    load_stim: process
      begin
        load_tb <= '0'; wait for 200 ns;
        load_tb <= '1'; d_tb <= "0101"; wait for 20 ns; d_tb <= "0101"; 
wait for 20 ns;
    end process;


end architecture;

von FPGA NOTFALLSEELSORGE (Guest)


Attached files:

Rate this post
useful
not useful
Christos Goulas wrote:
> I put a new value to d_tb as you can see

No, your value is 0101. All the time.

You can write the process as below:
1
load_stim: process
2
      begin
3
        load_tb <= '0';
4
    wait for 220 ns;
5
        load_tb <= '1';
6
    d_tb <= "1001";
7
    wait for 40 ns;
8
    load_tb <= '0';
9
    wait for 200 ns;
10
    load_tb <= '1';
11
    d_tb <= "0101";
12
    wait for 40 ns;
13
    load_tb <= '0';
14
    wait;
15
    end process;

von Salm@hmUd457! .. (almahmoud84)


Rate this post
useful
not useful
I can't understand this post, unable to understand.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig