mux2to1:

library ieee;
use ieee.std_logic_1164.all;

entity mux2to1 is
  port(in1, in2, sel: in std_logic;
     output: out std_logic);
end entity;

architecture bahavioral of mux2to1 is
  begin
    process(in1, in2, sel)
      begin
        case sel is
          when '0' => output <= in1;
          when others => output <= in2;
        end case;
    end process;
end architecture;

d flip flop:

library ieee;
use ieee.std_logic_1164.all;

entity dff is
  port(d, clock, reset: in std_logic;
     q: out std_logic);
end entity;

architecture behavioral of dff is
  begin
    process(clock, reset)
      begin
        if rising_edge(clock) then
          if reset = '1' then
            q <= '0';
          else
            q <= d;
          end if;
        end if;
    end process;
end architecture;

counter:

library ieee;
use ieee.std_logic_1164.all;

entity counter is
  port(clock, reset, load, enable: in std_logic;
     d: in std_logic_vector(3 downto 0);
     a: out std_logic_vector(3 downto 0);
     carry: out std_logic);
end entity;

architecture structural of counter is
  component mux2to1
    port(in1, in2, sel: in std_logic;
         output: out std_logic);
  end component;

  component dff
    port(d, clock, reset: in std_logic;
         q: out std_logic);
  end component;

  signal xor_out, and_out, q_out, mux_out: std_logic_vector(3 downto 0);

  begin
    block00: mux2to1 port map(in1 => xor_out(0), in2 => d(0), sel => 
load, output => mux_out(0));
    block01: mux2to1 port map(in1 => xor_out(1), in2 => d(1), sel => 
load, output => mux_out(1));
    block02: mux2to1 port map(in1 => xor_out(2), in2 => d(2), sel => 
load, output => mux_out(2));
    block03: mux2to1 port map(in1 => xor_out(3), in2 => d(3), sel => 
load, output => mux_out(3));
    block04: dff port map (d => mux_out(0), clock => clock, reset => 
reset, Q => Q_out(0));
    block05: dff port map (d => mux_out(1), clock => clock, reset => 
reset, Q => Q_out(1));
    block06: dff port map (d => mux_out(2), clock => clock, reset => 
reset, Q => Q_out(2));
    block07: dff port map (d => mux_out(3), clock => clock, reset => 
reset, Q => Q_out(3));
    xor_out(0) <= q_out(0) xor enable;
    xor_out(1) <= q_out(1) xor and_out(0);
    xor_out(2) <= q_out(2) xor and_out(1);
    xor_out(3) <= q_out(3) xor and_out(2);
    and_out(0) <= enable and q_out(0);
    and_out(1) <= and_out(0) and q_out(1);
    and_out(2) <= and_out(1) and q_out(2);
    and_out(3) <= and_out(2) and q_out(3);
    carry <= and_out(3);
    a <= q_out;

end architecture;


Above is the code for the counter. What I want is to implement a 
testbench. Below is the testbench that I have written. But the testbench 
is not working properly. The clock, reset, enable and load take values 
properly but the d is undefined. How can I do it work?

testbench

library ieee;
use ieee.std_logic_1164.all;

entity counter_tb is
end entity;

architecture counter_tb_arch of counter_tb is
  component counter
    port(clock, reset, load, enable: in std_logic;
        d: in std_logic_vector(3 downto 0);
        a: out std_logic_vector(3 downto 0);
        carry: out std_logic);
  end component;

  signal clock_tb, reset_tb, load_tb, enable_tb: std_logic;
  signal d_tb: std_logic_vector(3 downto 0);
  signal a_tb: std_logic_vector(3 downto 0);
  signal carry_tb: std_logic;

  begin

    dut: counter port map(clock => clock_tb,
                reset => reset_tb,
                load => load_tb,
                enable => enable_tb,
                d => d_tb,
                a => a_tb,
                carry => carry_tb);

    reset_stim: process
      begin
        reset_tb <= '1'; wait for 20 ns;
        reset_tb <= '0'; wait;
    end process;

    clock_stim: process
      begin
        clock_tb <= '0'; wait for 20 ns;
        clock_tb <= '1'; wait for 20 ns;
    end process;

    enable_stim: process
      begin
        enable_tb <= '0'; wait for 50 ns;
        enable_tb <= '1'; wait;
    end process;

    load_stim: process
      begin
        load_tb <= '0'; wait;
    end process;


end architecture;