ABEL to Verilog conversion

In your case it could help to read the XST-User Guide in the
Xilinx Software Manuals:
 -> Chapter 2: XST HDL Coding Techniques <-
 Xilinx has there a lot of hardware examples for VHDL/verilog.
here the verilog for a D-type rising clock edge flipflop:
>Flip-Flop With Positive-Edge Clock Verilog Coding Example
>//
>// Flip-Flop with Positive-Edge Clock
>//
>module v_registers_1 (C, D, Q);
>         input C, D;
>         output Q;
>  reg Q;
>always @(posedge C)
>   begin
>     Q <= D;
>   end
>endmodule

http://www.xilinx.com/itp/xilinx10/books/docs/xst/xst.pdf

Please Provide Verilog code for this

wow, cant believe that somebody was still willing to write cplds with 
ABEL.

I do not often write verilog, but here i make an exception. so this 
piece is just from scratch. test yourself and have fun!

imho, learn verilog or vhdl, it is worth it!

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module whatever (

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a, 

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d,

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WR,

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clk    , // Clock Input

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reset , // Reset input 

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out         // Q output

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);

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//-----------Input Ports---------------

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input [4:0] a; 

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input [7:0] d;

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input clk, reset,nWR; 

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//-----------Output Ports---------------

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output out;

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//------------Internal Variables--------

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reg q;

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wire N_SIG;

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//-------------Code Starts Here---------

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assign N_SIG = WR& A3& A2& ~A1&~A0& D7& D6&~D5&~D4

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always @ ( posedge clk or negedge reset)

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if (~reset) begin

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q <= 1'b0;

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end  else begin

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q <= N_FF& N_SIG& D3& ~D2& ~D1 & ~D0

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    | ~N_FF& N_SIG& D3&~D2&~D1& D0;

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end

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assign out = q;

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endmodule //End Of Module whatever

Hello to anybody out there listening-in accross the universe lolol. I 
have a couple of ABEL source and jed files that are compiled for the 
xc9500xl series of cpld. Can someone tell me if it is still possible to 
either compile for the xc9500 series (5v version chips), or if possible 
how to modify the jed files to fool jtag programming into believing the 
xl versions are present ?

Take a new topic for a new question!

Athos wrote:
> I
> have a couple of ABEL source and jed files that are compiled for the
> xc9500xl series of cpld. Can someone tell me if it is still possible to
> either compile for the xc9500 series (5v version chips), or if possible
> how to modify the jed files to fool jtag programming into believing the
> xl versions are present ?

Xilinx ISE before version 11.1 support Abel:
https://www.xilinx.com/support/answers/32354.html

Download ISE 10.1 and convert your Abel files to VHDL.

regards,
Duke

Please provide verilog code for this