Forum: FPGA, VHDL & Verilog ABEL to Verilog conversion

von Sutton Mehaffey (Guest)

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I've used Abel for many years on all kinds of projects.  The newer 
Xilinx IDEs no longer support Abel.  I still use the last version (10.5) 
that has the Abel compiler.  Obviously changing languages requires some 
type of learning curve.  But, I am thinking that I need to set aside 
some time to learn Verilog since that seems to be the language of choice 
these days in CPLD design.

Most of my projects use a CPLD as an address decode chip.  I was looking 
for different schemes for a simple Abel address decode conversion to 

A7..A0 pin 1,2,5,6,7,8,9,10;
ABUS = [A7..A0];
D0 pin 60;
WR pin 22;
DISPLAY_POWER_P pin 121 istype 'reg_D';

DISPLAY_POWER_P.clk = !WR & (ABUS == ^h33);

So, basically, this is a power line for a Display using a 'D' flip flop 
as a latch.  If ABUS = 0x33, WR is low, and D0 is high, the display 
turns on.  D0=0 turns the display off.  A reset button clears out the 

What is the correlating code in verilog to do the same thing?  I have 50 
or so exact configurations in my Abel code to turn on/off different 
things, using this exact same code scheme.  So, is this an easy 



von bko (Guest)

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In your case it could help to read the XST-User Guide in the
Xilinx Software Manuals:
 -> Chapter 2: XST HDL Coding Techniques <-
 Xilinx has there a lot of hardware examples for VHDL/verilog.
here the verilog for a D-type rising clock edge flipflop:
>Flip-Flop With Positive-Edge Clock Verilog Coding Example
>// Flip-Flop with Positive-Edge Clock
>module v_registers_1 (C, D, Q);
>         input C, D;
>         output Q;
>  reg Q;
>always @(posedge C)
>   begin
>     Q <= D;
>   end


von saravana bavananthan (Guest)

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Please Provide Verilog code for this

von Klakx (Guest)

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wow, cant believe that somebody was still willing to write cplds with 

I do not often write verilog, but here i make an exception. so this 
piece is just from scratch. test yourself and have fun!

imho, learn verilog or vhdl, it is worth it!
module whatever (
clk    , // Clock Input
reset , // Reset input 
out         // Q output
//-----------Input Ports---------------
input [4:0] a; 
input [7:0] d;
input clk, reset,nWR; 

//-----------Output Ports---------------
output out;

//------------Internal Variables--------
reg q;
wire N_SIG;

//-------------Code Starts Here---------
assign N_SIG = WR& A3& A2& ~A1&~A0& D7& D6&~D5&~D4

always @ ( posedge clk or negedge reset)
if (~reset) begin
q <= 1'b0;
end  else begin
q <= N_FF& N_SIG& D3& ~D2& ~D1 & ~D0
    | ~N_FF& N_SIG& D3&~D2&~D1& D0;
assign out = q;
endmodule //End Of Module whatever 


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