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Forum: FPGA, VHDL & Verilog ABEL to Verilog conversion


von Sutton Mehaffey (Guest)


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I've used Abel for many years on all kinds of projects.  The newer 
Xilinx IDEs no longer support Abel.  I still use the last version (10.5) 
that has the Abel compiler.  Obviously changing languages requires some 
type of learning curve.  But, I am thinking that I need to set aside 
some time to learn Verilog since that seems to be the language of choice 
these days in CPLD design.

Most of my projects use a CPLD as an address decode chip.  I was looking 
for different schemes for a simple Abel address decode conversion to 
Verilog.

A7..A0 pin 1,2,5,6,7,8,9,10;
ABUS = [A7..A0];
D0 pin 60;
WR pin 22;
RESET_BUTTON_N pin 122;
DISPLAY_POWER_P pin 121 istype 'reg_D';

DISPLAY_POWER_P.clk = !WR & (ABUS == ^h33);
DISPLAY_POWER_P := D0;
DISPLAY_POWER_P.ar = !RESET_BUTTON_N;

So, basically, this is a power line for a Display using a 'D' flip flop 
as a latch.  If ABUS = 0x33, WR is low, and D0 is high, the display 
turns on.  D0=0 turns the display off.  A reset button clears out the 
latch.

What is the correlating code in verilog to do the same thing?  I have 50 
or so exact configurations in my Abel code to turn on/off different 
things, using this exact same code scheme.  So, is this an easy 
conversion?

Thanks.

Sutton

von bko (Guest)


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In your case it could help to read the XST-User Guide in the
Xilinx Software Manuals:
 -> Chapter 2: XST HDL Coding Techniques <-
 Xilinx has there a lot of hardware examples for VHDL/verilog.
here the verilog for a D-type rising clock edge flipflop:
>Flip-Flop With Positive-Edge Clock Verilog Coding Example
>//
>// Flip-Flop with Positive-Edge Clock
>//
>module v_registers_1 (C, D, Q);
>         input C, D;
>         output Q;
>  reg Q;
>always @(posedge C)
>   begin
>     Q <= D;
>   end
>endmodule

http://www.xilinx.com/itp/xilinx10/books/docs/xst/xst.pdf

von saravana bavananthan (Guest)


Attached files:

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Please Provide Verilog code for this

von Klakx (Guest)


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wow, cant believe that somebody was still willing to write cplds with 
ABEL.

I do not often write verilog, but here i make an exception. so this 
piece is just from scratch. test yourself and have fun!

imho, learn verilog or vhdl, it is worth it!
1
module whatever (
2
a, 
3
d,
4
WR,
5
clk    , // Clock Input
6
reset , // Reset input 
7
out         // Q output
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);
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//-----------Input Ports---------------
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input [4:0] a; 
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input [7:0] d;
12
input clk, reset,nWR; 
13
14
//-----------Output Ports---------------
15
output out;
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//------------Internal Variables--------
18
reg q;
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wire N_SIG;
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//-------------Code Starts Here---------
22
assign N_SIG = WR& A3& A2& ~A1&~A0& D7& D6&~D5&~D4
23
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always @ ( posedge clk or negedge reset)
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if (~reset) begin
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q <= 1'b0;
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end  else begin
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q <= N_FF& N_SIG& D3& ~D2& ~D1 & ~D0
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    | ~N_FF& N_SIG& D3&~D2&~D1& D0;
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end
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assign out = q;
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endmodule //End Of Module whatever

von Athos (Guest)


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Hello to anybody out there listening-in accross the universe lolol. I 
have a couple of ABEL source and jed files that are compiled for the 
xc9500xl series of cpld. Can someone tell me if it is still possible to 
either compile for the xc9500 series (5v version chips), or if possible 
how to modify the jed files to fool jtag programming into believing the 
xl versions are present ?

von Duke Scarring (Guest)


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Take a new topic for a new question!

Athos wrote:
> I
> have a couple of ABEL source and jed files that are compiled for the
> xc9500xl series of cpld. Can someone tell me if it is still possible to
> either compile for the xc9500 series (5v version chips), or if possible
> how to modify the jed files to fool jtag programming into believing the
> xl versions are present ?

Xilinx ISE before version 11.1 support Abel:
https://www.xilinx.com/support/answers/32354.html

Download ISE 10.1 and convert your Abel files to VHDL.

regards,
Duke

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