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Forum: FPGA, VHDL & Verilog


Programmable logic


Subject Author Replies Last post
sticky FPGA development resources Andreas S. 15
HELP-VHDL-CODE Merima D. 7
Microsemi Smartfusion2 i²C Setup Allfred 0
unexpected behavior of non-blocking assignment in an priority arbiter Jimmy Z. 5
Error creating Nios II application and BSP from template Nasas Kycas 6
washing machine (fsm) controller Jad F. 5
Knight Rider VHDL Elton Saraçi 3
Display binary image on vga using VHDL ElectroCataru 5
Index Input for Encoder Interface SparkyT 10
Compile warnings in model sim Peter Reitinger 4
SDRAM read problem 94onur94 1
get some outputsignals if cnt reaches an exact amount Steven Tumler 2
How to implement lookup table in VHDL Were to lookup? 5
ABEL to Verilog conversion Sutton Mehaffey 5
Initializing simulation with data from ILA Poor and lonely unused sequential element 2
Moving a square on VGA monitor VHDL Cristina E. 3
Error when running modelsim Mart Bent 6
Clock domain crossing Stefania M. 7
VHDL Blinking leds James H. 2
gps nmea design using verilog Dammrr R. 11
counter with signal enable (active high) and synchronous reset signal (active high) Juan 2
adc with fpga interface niclas 8
Error loading design (Modelsim student version) Keltuzad 54
Double Data Rate Serializer verilog Atalin 3
simbol moving using buttons cataru 1
Abel to VHDL Jose 3
Image processing in Verilog - simulation yk_learner 2
help in reading a large text file using verilog. Alangs Kannan 17
is it possible for bcd to ascii module? John B. 7
for loop in verilog code nelson george 20
Verilog: # Error loading design Vasily D. 1
Can anyone help me to solve this verilog(beginner) question or suggest me any source for solving Omar K. 1
beginner question on gate level d flip flop simulation Jimmy Z. 1
ice40HX8k enable signal from clock Fabian 1
How to properly multiply signed and unsigned signed unsigned 1
Synthesis: Mix of sync and async assignments to register if else what when 5
Determining trace delay for input delay constraints Timing violation 13
Enhanced Tiger Single Board Computer Myron P. 3
Getting to the Root Cause of BGA Assembly Problems smartronics 1
How powerful is Verilog at using parameters to specify designs? Kevin S. 0
warning: Static variable initialization requires explicit lifetime in this context Kevin S. 2
Serializer verilog Atalin 9
Error in Loading Design NAZMUL HASAN 1
Input/feedback regarding desing using statemachine (VHDL) Lu F. 3
Gray counter verilog Gio97 6
What file suffix is usually used for the filename following a -o? Kevin S. 1
Is there anything beyond the Palnitkar book? Kevin S. 2
Right shift with VHDL Alex 7
Can anyone explain "cannot currently create a parameter of type" compilation error message? Kevin S. 0
In Verilog, why can't I compare my (genvar) with an integer value in my (for) loop? Kevin S. 3
Why can't I set a (genvar) outside the control section of a loop? Kevin S. 4
Can a function take a boolean argument? Kevin S. 5