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Forum: FPGA, VHDL & Verilog


Programmable logic


Subject Author Replies Last post
sticky FPGA development resources Andreas S. 6
Error loading design (Modelsim student version) Keltuzad 41
gpio pull-down demsp 1
Verilog Code for 4 32 bit numbers sorting in Ascending order Chaitanya Bommu 9
Altera Cyclone IV Internal Memory - ROM: 1-Port Problem Adrian H. 2
pass transistor Dong Wang 26
System Verilog alarm clock Andrew M. 0
Dueprologic Cyclone iv fpga dev board Hareesh M. 5
VHDL (GHDL): can't have multiple entities in file? Edmund 13
BITSLIP FUNCTION STATEMACHINE atif 0
pass transistor logic monish 1
SPI slave design idea? Jack BK 25
TCS34725 Basys3 VHDL kimsinki 0
Modifying a PCA955 vhdl code Guest 2
How To Read A SD Card Adrian H. 6
FPGA Algorithms and Applications in the IoT, AI, and High-Performance Computing - Invitation to Edit Daniel N. 0
Sending and receiving somme data within FPGA Mafah M. 4
eye scan (eye diagram) kamal 1
Green/Red detector and button controlled car (BASYS3/VHDL) kilimci 1
VHDL - RTL design references George R. 2
how to do testbench nadirah 5
VGA 640x480 project Adrian H. 9
Neural Network on Xilinx Virtex 5 Electronics_hobbyist E. 9
4 bit ALU variable name question Andrew M. 1
Servomotor. PWM and VHDL Soko Loko 12
Manual Clock Aldemaro G. 0
Comments on: Beitrag "Re: Erfahrung mit SPI Slave und Spartan 6 FPGA?" SparkyT 5
Vhdl time window Luca M. 15
VHDL output signal in hexadecimal instead of binary Guest 3
FIFO MEMORY VHDL Patryk S. 17
Duty and phase control clock divider Greg W. 2
cobverting 64 bit to 32 bit. slim_pga 6
Viscometer vhdl Emil Lagrange 2
Matrix Display Josip J. 2
force input in simulation wrong. fuck_modelsim 2
vhdl code to find max value of stream of unsigned 8 bit values Jeevan R. 2
decoder in vhdl dont work in simulation. ee_vhdl 5
Keeping Hierarchy in post-layout simulation using Microsemi designer Daveburton D. 1
Rising and falling edges Bob T. 1
BlocklyVHDL visual VHDL editor Hans 3
Generating SAIF file dayana42200 1
Testing I2C on cyclone 2 board Hareesh M. 12
Quartus II: How to disable most synthesis optimizations options Johannes 0
Verilog help MUHAMMAD FARHAN 1
Barrel Shifter Omar 7
fixed combo logic Bogdan 2
Problem with ultrasonic sensor, Luis Alfredo 1
UART RECEIVER Hareesh M. 7
method for modeling circuit Mohammad Mothermohammad 7
UART transmitter Hareesh M. 16
** Error: (vcom-66) Execution of vlib failed. Please check the error log for more details. Amalia 1
Scrolling a text on a 7-seg display Giorgia 3