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Forum: FPGA, VHDL & Verilog


Programmable logic


Subject Author Replies Last post
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Compile warnings in model sim Peter Reitinger 4
SDRAM read problem 94onur94 1
get some outputsignals if cnt reaches an exact amount Steven Tumler 2
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Initializing simulation with data from ILA Poor and lonely unused sequential element 2
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Error when running modelsim Mart Bent 6
Clock domain crossing Stefania M. 7
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Can anyone help me to solve this verilog(beginner) question or suggest me any source for solving Omar K. 1
beginner question on gate level d flip flop simulation Jimmy Z. 1
ice40HX8k enable signal from clock Fabian 1
How to properly multiply signed and unsigned signed unsigned 1
Synthesis: Mix of sync and async assignments to register if else what when 5