Forum: FPGA, VHDL & Verilog

Programmable logic

Subject Author Replies Last post
sticky FPGA development resources Andreas Schwarz 4
NAND with x input LE DUC LOC 0
Altera ALTCHIP_ID andi6510 0
LUT Questions Abdeljalil Bounaime 13
Simple question about a case statement Luis Gonzalez 1
VHDL project : 5 bit shift reg Michael 42
PS/2 module with LCD Luis Gonzalez 5
If or else if? Which is faster? techno-rogue 8
Vivado warning for RAM component Tudor Ioan 2
output comes after 1.2 sec delay after Power ON Naveedishtiaq Naveed 4
Error when trying to synthesize Tudor 5
sdram problem in vhdl quartus Vehbi Baycan 2
VHDL looping query Ana Ana 1
Verilog Simple SPI Code? Ferhat YOL 5
Error (10349): VHDL Association List error at bin_7seg_tester.vhd(13): formal "bin" does not exist Emil 1
Verilog-Range must be bounded by constant expressions Akshay E. 2
Ethernet: No data useful on eth_rxd (Arty Board) Jonas 9
Not a homework question, I am 58 1/2! Julian Mortimer 1
Synchronization logic for DAQ IP Viya Vijayan 1
effitient code nick 7
VHDL error “Process clocking is too complex.” Rocking Sharma 3
Multi functional push key. Fue Xiong 4
fpga for solar inverter and power electronics Mah Fhg 3
set_input_delay And set_output_delay .SDC Constraints Ahmed Abbasi 0
Maximum current rating Viya Vijayan 0
Petalinux + lwIP Stack - no tcp connection Petalinux + lwIP Stack - no tcp connection 0
for loop and addition Yoni Cohen 7
locked help in image processing using verilog Alangs Kannan 7
ADC-DAC spartan 3e vhdl code John Daniel 3
FSM coding in VHDL Tarun Mittal 2
no interface for function call, slice or indexed name in association amir 1
array of an entity amir 2
File system in vivado SDK Sai Shashi 4
32-bit adder question DSP_Arch_Student 4
Writing Testbench for Bidirectional/Inout Port Ahmed Abbasi 3
Warning: NUMERIC_STD.">=": metavalue detected felix 2
Is it possible to create own messages in xilinx Christin Kimeri 3
Error problem newProgrammer 1
Verilog synthesis - Too many always blocks, or too long datapath or? Zwergi 4
Problem synthesizing in Vivado Julian Mortimer 3
problem in writing and reading from DDR3 in zed board Sai Shashi 6
Resizing an image on FPGA Harvey 3
Generating a square wave from input push button Calibroflower 3
Error loading design (Modelsim student version) Keltuzad 24
Reconfigure MachX02 using Wishbone Felix Seidel 0
locked A FPGA Programer Abolfazl Mazloomi 8
Creating Multi Files Christin Kimeri 6
Which programmator? Andrzej Borucki 3
modelsim simulaiton KAYHAN ÇELİK 5
Flash Memory Christin Kimeri 2
Testbench for 8b/10b encoder verilog code ? Christy Philip 5
remains a black-box since it has no binding entity Kim 5