EmbDev.net

Forum: FPGA, VHDL & Verilog


Programmable logic


Subject Author Replies Last post
sticky FPGA development resources Andreas S. 7
How to use USB port of FPGA to access webcam Lakshita J. 3
How can I make array length the logarithm of an input parameter in Verilog? Kevin S. 1
UART + FIFO transmission problems Alessandro 8
Can size of a port be input as a parameter? Kevin S. 1
Can a Verilog function return an array indexed from one to a value passed as an input parameter? Kevin Simonson 1
How can I declare local variables in a Verilog task or function? Kevin Simonson 1
Vivado HLS experiences with Zynq boards Zoltán L. 4
text mode vga Sizeofrawdata S. 6
updating FPGA firmware in the field Eugene 6
VHDL write to specific memory address Robert R. 2
Vhdl clockdivider Kadir A. 5
Digital clock 7-seg display NEXYS-3 peterkraft 5
VHDL Testbench Process Issue Josef F. 4
sine wave in vhdl Sheikh S. 5
N samples from an ADC Aron L. 3
clocking module in vivado? Flat B. 1
what kind of memory should i use? Flat B. 5
Write in a file with verilog XaBla 2
help writing testbench for uart mike 6
BITSLIP FUNCTION STATEMACHINE atif 1
How can I add the status of lights “red-yellow” in Verilog Michał W. 1
Reusing registers in VHDL FSM code Darian Reyes 3
Keypad saved shifting display in Verilog Cm Y. 0
register clear on read vhdl 3
VHDL code for booth multiplier mike 11
how to open a ready project inside library work in modelsim ee_vhdl 2
PWM with 4-bits control in Verilog Cm Y. 13
ULX3S powerful ECP5 board for open source FPGA Goran M. 0
Project System Password Autielli Mako 1
Error loading design (Modelsim student version) Keltuzad 43
Wifi audio hub Chaminda J. 8
Code VHDL/Verilog Spartan 3E - Solar Panel Freddy S. 2
ws2812 vhdl problem Flat B. 4
Verilog Code for 4 32 bit numbers sorting in Ascending order Chaitanya Bommu 10
Variable clock with prescaler? Mohamed H. 2
How to connect an external FIFO to FPGA Charlie H. 1
fpga soartan 6 io pins are no longer working ahmeddarwish 0
Increase the frequency abdelhak taamouch 2
gpio pull-down demsp 2
$fwrite usage clarification Andrew M. 0
Problem with Writing a SDRAM Controller Mehdi 1
Altera Cyclone IV Internal Memory - ROM: 1-Port Problem Adrian H. 2
pass transistor Dong Wang 29
System Verilog alarm clock Andrew M. 1
Dueprologic Cyclone iv fpga dev board Hareesh M. 5
pass transistor logic monish 1
SPI slave design idea? Jack BK 25
TCS34725 Basys3 VHDL kimsinki 0
Modifying a PCA955 vhdl code Guest 2
How To Read A SD Card Adrian H. 6
FPGA Algorithms and Applications in the IoT, AI, and High-Performance Computing - Invitation to Edit Daniel N. 0