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Forum: FPGA, VHDL & Verilog
Programmable logic
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Subject
Author
Replies
Last post
FPGA development resources
Andreas S.
15
2020-12-27 12:31
How to implement lookup table in VHDL
Were to lookup?
5
2021-02-24 10:41
ABEL to Verilog conversion
Sutton Mehaffey
5
2021-02-12 12:01
Initializing simulation with data from ILA
Poor and lonely unused sequential element
2
2021-01-19 18:43
Moving a square on VGA monitor VHDL
Cristina E.
3
2021-01-10 20:49
Error when running modelsim
Mart Bent
6
2021-01-07 01:23
Clock domain crossing
Stefania M.
7
2021-01-06 08:19
VHDL Blinking leds
James H.
2
2021-01-05 23:15
gps nmea design using verilog
Dammrr R.
11
2021-01-04 17:09
counter with signal enable (active high) and synchronous reset signal (active high)
Juan
2
2020-12-27 21:38
adc with fpga interface
niclas
8
2020-12-23 18:24
Error loading design (Modelsim student version)
Keltuzad
54
2020-12-14 16:19
Double Data Rate Serializer verilog
Atalin
3
2020-12-05 06:50
simbol moving using buttons
cataru
1
2020-12-02 14:44
Abel to VHDL
Jose
3
2020-12-01 21:07
Image processing in Verilog - simulation
yk_learner
2
2020-11-20 06:08
help in reading a large text file using verilog.
Alangs Kannan
17
2020-11-19 09:45
is it possible for bcd to ascii module?
John B.
7
2020-11-05 13:02
for loop in verilog code
nelson george
20
2020-11-02 03:08
Verilog: # Error loading design
Vasily D.
1
2020-10-26 11:01
Can anyone help me to solve this verilog(beginner) question or suggest me any source for solving
Omar K.
1
2020-10-22 19:19
Index Input for Encoder Interface
SparkyT
5
2020-10-09 08:26
beginner question on gate level d flip flop simulation
Jimmy Z.
1
2020-10-09 06:18
ice40HX8k enable signal from clock
Fabian
1
2020-10-02 17:14
How to properly multiply signed and unsigned
signed unsigned
1
2020-10-02 09:08
Synthesis: Mix of sync and async assignments to register
if else what when
5
2020-10-01 08:27
Determining trace delay for input delay constraints
Timing violation
13
2020-09-29 10:40
Enhanced Tiger Single Board Computer
Myron P.
3
2020-09-25 04:56
Getting to the Root Cause of BGA Assembly Problems
smartronics
1
2020-09-22 12:44
How powerful is Verilog at using parameters to specify designs?
Kevin S.
0
2020-09-22 00:21
warning: Static variable initialization requires explicit lifetime in this context
Kevin S.
2
2020-09-19 20:49
Serializer verilog
Atalin
9
2020-09-17 14:04
Error in Loading Design
NAZMUL HASAN
1
2020-09-10 18:50
Input/feedback regarding desing using statemachine (VHDL)
Lu F.
3
2020-09-07 15:48
Gray counter verilog
Gio97
6
2020-09-05 16:19
What file suffix is usually used for the filename following a -o?
Kevin S.
1
2020-09-04 01:54
Is there anything beyond the Palnitkar book?
Kevin S.
2
2020-09-02 22:18
Right shift with VHDL
Alex
7
2020-08-29 16:29
Can anyone explain "cannot currently create a parameter of type" compilation error message?
Kevin S.
0
2020-08-28 21:07
In Verilog, why can't I compare my (genvar) with an integer value in my (for) loop?
Kevin S.
2
2020-08-27 22:52
Why can't I set a (genvar) outside the control section of a loop?
Kevin S.
4
2020-08-27 22:45
Can a function take a boolean argument?
Kevin S.
5
2020-08-22 22:07
Is it illegal to use an (enum) as a function input?
Kevin S.
0
2020-08-22 21:05
Having trouble understanding warnings and syntax errors in my Verilog.
Kevin S.
2
2020-08-21 03:07
How do I declare a packed array in Verilog?
Kevin S.
3
2020-08-19 17:41
Implement a VHDL program using with select for PAL
James
2
2020-08-17 01:06
Cannot get icarus to recognize enum or struct.
Kevin S.
2
2020-08-12 22:59
Free workshop materials: Integrating ARM Cortex M Processors into Xilinx FPGAs
Alex W.
6
2020-08-08 00:08
Double registering
SparkyT
4
2020-08-06 14:45
Step-by-Step Xilinx Vitis Getting Started Guides
Alex W.
0
2020-08-06 08:40
ISE synthesis warning
changseon
1
2020-07-23 07:48
Booth Multiplier Verilog code not working
Prabhanshu
3
2020-07-22 15:50
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