Forum: FPGA, VHDL & Verilog

Programmable logic

Subject Author Replies Last post
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vcom-1576 error with expecting BEGIN SilentRoar 5
*HELP VHDL CODE * MariosBon 19
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Index Input for Encoder Interface SparkyT 10
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SDRAM read problem 94onur94 1
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Initializing simulation with data from ILA Poor and lonely unused sequential element 2
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Clock domain crossing Stefania M. 7
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counter with signal enable (active high) and synchronous reset signal (active high) Juan 2
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help in reading a large text file using verilog. Alangs Kannan 17
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for loop in verilog code nelson george 20
Verilog: # Error loading design Vasily D. 1
Can anyone help me to solve this verilog(beginner) question or suggest me any source for solving Omar K. 1
beginner question on gate level d flip flop simulation Jimmy Z. 1
ice40HX8k enable signal from clock Fabian 1
How to properly multiply signed and unsigned signed unsigned 1
Synthesis: Mix of sync and async assignments to register if else what when 5
Determining trace delay for input delay constraints Timing violation 13
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How powerful is Verilog at using parameters to specify designs? Kevin S. 0
warning: Static variable initialization requires explicit lifetime in this context Kevin S. 2
Serializer verilog Atalin 9
Error in Loading Design NAZMUL HASAN 1
Input/feedback regarding desing using statemachine (VHDL) Lu F. 3
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What file suffix is usually used for the filename following a -o? Kevin S. 1