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Forum: FPGA, VHDL & Verilog


Programmable logic


Subject Author Replies Last post
sticky FPGA development resources Andreas Schwarz 4
Wrong syntax near Cergey Chaulin 1
Xilinx BRAM behaviour query. Julian Mortimer 0
Problem synthesizing in Vivado Julian Mortimer 4
Xilinx's RAM Joey Weyland 0
FPGA design engineer MONAL THORAT 0
Interfacing rotary encoder with Spartan 3 E Nirav Bhatt 0
Connect FPGA with i2c to a mikrocontroller ki92 2
Logarithm Calculator John Hardy 8
ADC/DAC Spartan 3E VHDL code problem Irati 4
Implementing Recast block in FPGA. Japa 1
send UDP packets from FPGA meleneemil 15
ERROR:HDLCompiler:1440 : Non-constant loop condition not supported for for TienNguyen 2
UCF Motor Stepper On FPGA SPARTAn 3E with Driver L 293 Freddy Silaban 12
Excess 3 to gray code using verilog Kamal 0
Use of rotary encoder in Spartan 3E Nirav Bhatt 2
RTL technique about "for" combine murakami 1
LVDS Controller LCD Panel nairolf_sch 2
Use I2C Core on DE0? Mo 1
qsys and user design mike 2
Assignment under elsif does not work Burak Güneş 5
Verilog with FSM Rytis 1
Programmable SoC and SoC FPGA Abdeljalil Bounaime 1
locked Interleaver/deinterleaver VHDL Syed Imam 9
NAND with x input LE DUC LOC 1
Altera ALTCHIP_ID andi6510 0
LUT Questions Abdeljalil Bounaime 13
Simple question about a case statement Luis Gonzalez 1
VHDL project : 5 bit shift reg Michael 42
PS/2 module with LCD Luis Gonzalez 5
If or else if? Which is faster? techno-rogue 8
Vivado warning for RAM component Tudor Ioan 2
output comes after 1.2 sec delay after Power ON Naveedishtiaq Naveed 4
Error when trying to synthesize Tudor 5
sdram problem in vhdl quartus Vehbi Baycan 2
VHDL looping query Ana Ana 1
Verilog Simple SPI Code? Ferhat YOL 5
Error (10349): VHDL Association List error at bin_7seg_tester.vhd(13): formal "bin" does not exist Emil 1
Verilog-Range must be bounded by constant expressions Akshay E. 2
Ethernet: No data useful on eth_rxd (Arty Board) Jonas 9
Not a homework question, I am 58 1/2! Julian Mortimer 1
Synchronization logic for DAQ IP Viya Vijayan 1
effitient code nick 7
VHDL error “Process clocking is too complex.” Rocking Sharma 3
Multi functional push key. Fue Xiong 4
fpga for solar inverter and power electronics Mah Fhg 3
set_input_delay And set_output_delay .SDC Constraints Ahmed Abbasi 0
Maximum current rating Viya Vijayan 0
Petalinux + lwIP Stack - no tcp connection Petalinux + lwIP Stack - no tcp connection 0
for loop and addition Yoni Cohen 7
locked help in image processing using verilog Alangs Kannan 7
ADC-DAC spartan 3e vhdl code John Daniel 3