I'm trying to write a simple program in vhdl that is based on clock.
When I have a rising edge of the clock , i want to get at the out bit a
and b. And when I have falling _edge I want to get 0 at the output.
But when I run it in Modelsim program I see only one clock.
How can i see few clocks (for example 10 clocks)
Thank you very much.
I wrote the following code:
entity D_flip is
a: in std_logic;
b: in std_logic;
clk: in std_logic;
architecture flip of D_flip is
if rising_edge(clk) then
q<=a and b;
if falling_edge(clk) then