Hello everyone,
I'm trying to write a simple program in vhdl that is based on clock.
When I have a rising edge of the clock , i want to get at the out bit a
and b. And when I have falling _edge I want to get 0 at the output.
But when I run it in Modelsim program I see only one clock.
How can i see few clocks (for example 10 clocks)
Thank you very much.
I wrote the following code:
1  library ieee;

2  use ieee.std_logic_1164.all;

3  entity D_flip is

4  port(

5  a: in std_logic;

6  b: in std_logic;

7  clk: in std_logic;

8  q:out std_logic

9  
10  );

11  end D_flip;

12  
13  
14  architecture flip of D_flip is

15  
16  begin

17  process(clk)

18  begin

19  if rising_edge(clk) then

20  q<=a and b;

21  if falling_edge(clk) then

22  q<='0';

23  end if;

24  end process;

25  end flip;
