Hello everyone,
I'm trying to write a simple program in vhdl that is based on clock.
When I have a rising edge of the clock , i want to get at the out bit a 
and b. And when I have falling _edge I want to get 0 at the output.
But when I run it in Modelsim program I see only one clock.
How can i see few clocks (for example 10 clocks)
Thank you very much.
I wrote the following code:

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library ieee;

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use ieee.std_logic_1164.all;

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entity D_flip is

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port( 

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a: in std_logic;

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b: in std_logic;

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clk: in std_logic;

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q:out std_logic

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);

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end D_flip;

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architecture flip of D_flip is

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begin

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process(clk)

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begin

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if rising_edge(clk) then

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q<=a and b;

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if falling_edge(clk) then

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q<='0';

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end if;

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end process;

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end flip;