Forum: FPGA, VHDL & Verilog

Programmable logic

Subject Author Replies Last post
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RCA Testbench returns XXXXXXXX for 32 bit adder Hakim M. 3
VHDL: BCD to Sevensegment Tobias Hagenaars 6
The never seen SBC + FPGA board- VAAMAN! Vicharak 1
ModelSim memory allocation failure FPGA guy 11
How to add two signals of type std_logic Ashok M. 5
Interfacing 4x4 keypad with 16x2 LCD on FPGA using VHDL Sebastian M. 1
How to implement lookup table in VHDL Were to lookup? 7
Adding a Reset reduces used LE's by 35% Karsten F. 21
gnerating data flow diagrams from c code James Yunker 6
Verilog Code for 4 32 bit numbers sorting in Ascending order Chaitanya Bommu 14
How to use FPGA to drive TFT LCD Cliff W. 10
Synchronous two PWM signals generator Stas I. 3
Optimising size and speed Muhammad Tahir R. 5
I need to clarify a question about verilog Black 6
HELP- VHDL model of the PULSE TIMER Sandra L. 2
Read Bitmap Color depth 4 Bits Guest 6
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locked VHDL Projekt Guest 3
VHDL project Paul 11
package and procedure Dang T. 2
Executing ONERROR command at macro ./halfadder_simu.do line 6 RAMA 1
Error loading design (Modelsim student version) Keltuzad 64
Types do not match between component and entity at Simulation on Modelsim Nima 8
vcom-1576 error with expecting BEGIN SilentRoar 5
*HELP VHDL CODE * MariosBon 19
Help creating a SPI state machine in VHDL Michael N. 2
Led matrix VHDL Nathex 12
Microsemi Smartfusion2 i²C Setup Allfred 0
unexpected behavior of non-blocking assignment in an priority arbiter Jimmy Z. 5
Error creating Nios II application and BSP from template Nasas Kycas 7
washing machine (fsm) controller Jad F. 5
Knight Rider VHDL Elton Saraçi 3
Display binary image on vga using VHDL ElectroCataru 5
Index Input for Encoder Interface SparkyT 10
Compile warnings in model sim Peter Reitinger 4
SDRAM read problem 94onur94 1
get some outputsignals if cnt reaches an exact amount Steven Tumler 2
ABEL to Verilog conversion Sutton Mehaffey 5
Initializing simulation with data from ILA Poor and lonely unused sequential element 2
Moving a square on VGA monitor VHDL Cristina E. 3
Error when running modelsim Mart Bent 6
Clock domain crossing Stefania M. 7
VHDL Blinking leds James H. 2
gps nmea design using verilog Dammrr R. 11
counter with signal enable (active high) and synchronous reset signal (active high) Juan 2
adc with fpga interface niclas 9
Double Data Rate Serializer verilog Atalin 3
simbol moving using buttons cataru 1
Abel to VHDL Jose 3
Image processing in Verilog - simulation yk_learner 2