I have a task to implement adaptive huffman algorithm in vhdl. In the program i have to deal with some registers including one for the output of variable bit length. Some times the output will be in 128 bits. Some other time my output length will be 60 bits. Sometimes 200 bits.. So on. The output bit length will depend on the input symbols and its repeated occurance. So there are so many possible bit lengths for my output. In that case how can i write my output register with variable bit length. Like can i write it as Output : encoded_out( i down to 0); i can be optained from program.. Like that.. Is this possible????
You just need an additional register for the valid length...
Robin wrote: > Like can i write it as > Output : encoded_out( i down to 0); > i can be optained from program.. Like that.. Is this possible???? What happens when you try it? Of course you cannot change the "length" of a output vector dynamically, because simply imagine those outputs bits would be connectoed to FPGA pins. Should the FPGA dynamically shrink and expand as change a digital value? Ok, having got that the reslut is fairly easy: as port you use the broadest result-vector you will ever need (here it was 200 bits) and then you add a second vector (let it be the i-vector) that tells how much (or what part) of that result-vector is the valid result.
: Edited by Moderator