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Forum: FPGA, VHDL & Verilog Making a counter using VHDL

von Eric J. (coderic)

2022-03-11 07:23

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I want to make a counter that on every rising clock edge, adds 1 to my 
'counter' out and resets on a rising edge if 'reset = 1'. I had problems 
with working directly on the 'counter', so I have the extra signal 
'countr' as a temp.
However, when I run that code, it only adds 1 every two rising edges. 
Can someone explain why?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Counter is
    clk : in std_logic;
    reset : in std_logic;
    count : out std_logic_vector(3 downto 0)
end Counter;
architecture rtl of Counter is
signal countr : std_logic_vector(3 downto 0);
    process(clk)
    begin
        if(rising_edge(clk)) then
            countr <= std_logic_vector(to_unsigned(to_integer(unsigned(countr)) + 1, 4));
            if(reset = '1') then
                countr <= (others => '0');
            end if;
        end if;
        count <= countr;
    end process;
end architecture rtl;

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Re: Making a counter using VHDL

von Duke Scarring (Guest)

2022-03-11 07:31

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The assignment count <= countr is inside the process, which is only 
activated by simulator when the clk signal changes (see sensitivity 
list).

Just write it outside the process:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Counter is
    clk : in std_logic;
    reset : in std_logic;
    count : out std_logic_vector(3 downto 0)
end entity Counter;
architecture rtl of Counter is
    signal countr : unsigned(3 downto 0);
    process(clk)
    begin
        if(rising_edge(clk)) then
            countr <= countr + 1;
            if reset = '1' then
                countr <= (others => '0');
            end if;
        end if;
    end process;
    count <= std_logic_vector( countr);
end architecture rtl;