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Forum: FPGA, VHDL & Verilog Making a counter using VHDL


von Eric J. (coderic)


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I want to make a counter that on every rising clock edge, adds 1 to my 
'counter' out and resets on a rising edge if 'reset = 1'. I had problems 
with working directly on the 'counter', so I have the extra signal 
'countr' as a temp.
However, when I run that code, it only adds 1 every two rising edges. 
Can someone explain why?
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity Counter is
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port (
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    clk : in std_logic;
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    reset : in std_logic;
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    count : out std_logic_vector(3 downto 0)
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);
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end Counter;
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architecture rtl of Counter is
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signal countr : std_logic_vector(3 downto 0);
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begin
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    process(clk)
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    begin
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        if(rising_edge(clk)) then
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            countr <= std_logic_vector(to_unsigned(to_integer(unsigned(countr)) + 1, 4));
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            if(reset = '1') then
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                countr <= (others => '0');
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            end if;
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        end if;
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        count <= countr;
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    end process;
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end architecture rtl;

von Duke Scarring (Guest)


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The assignment count <= countr is inside the process, which is only 
activated by simulator when the clk signal changes (see sensitivity 
list).

Just write it outside the process:
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity Counter is
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port (
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    clk : in std_logic;
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    reset : in std_logic;
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    count : out std_logic_vector(3 downto 0)
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);
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end entity Counter;
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architecture rtl of Counter is
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    signal countr : unsigned(3 downto 0);
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begin
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    process(clk)
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    begin
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        if(rising_edge(clk)) then
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            countr <= countr + 1;
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            if reset = '1' then
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                countr <= (others => '0');
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            end if;
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        end if;
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    end process;
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    count <= std_logic_vector( countr);
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end architecture rtl;

Duke

von Eric J. (coderic)


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Many thanks, that did the trick!

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