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Forum: FPGA, VHDL & Verilog Accessing dut variables in testbench : VHDL


von Muhammad Tahir R. (Company: Self) (tahirsengine)


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Hey gals and guys,

So all I want is to access the "sw" from testbench and check it for a 
certain value. I do it regularly in Verilog, but this VHDL is a little 
harsh on me. Just see the "assert_test" process below. There in second 
assert expression I tried to do that, but still no success. Any 
soloutions to this situations?

-------------------------------------------------------------
Entity
-------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- FPGA projects using Verilog code VHDL code
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-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
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-- VHDL project: VHDL code for counters with testbench  
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-- VHDL project: VHDL code for up counter   
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entity UP_COUNTER is
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    Port ( clk: in std_logic; -- clock input
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           reset: in std_logic; -- reset input 
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           counter: out std_logic_vector(3 downto 0) -- output 4-bit counter
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     );
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end UP_COUNTER;
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architecture Behavioral of UP_COUNTER is
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signal counter_up: std_logic_vector(3 downto 0);
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signal sw: std_logic;
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begin
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-- up counter
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process(clk)
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begin
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if(rising_edge(clk)) then
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    if(reset='1') then
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         counter_up <= x"0";
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         sw <= '0';
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    else
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        counter_up <= counter_up + x"1";
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        sw <= '1';
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    end if;
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 end if;
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end process;
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 counter <= counter_up;
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end Behavioral;
-----------------------------------------------------------
Testbench
-----------------------------------------------------------
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-- Code your testbench here
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-- or browse Examples
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- FPGA projects using Verilog code VHDL code
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-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
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-- VHDL project: VHDL code for counters with testbench  
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-- VHDL project: Testbench VHDL code for up counter
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entity tb_counters is
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end tb_counters;
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architecture Behavioral of tb_counters is
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component UP_COUNTER 
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    Port ( clk: in std_logic; -- clock input
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           reset: in std_logic; -- reset input 
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           counter: out std_logic_vector(3 downto 0) -- output 4-bit counter
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     );
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end component;
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signal reset,clk, en: std_logic;
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signal counter:std_logic_vector(3 downto 0);
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begin
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dut: UP_COUNTER port map (clk => clk, reset=>reset, counter => counter);
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   -- Clock process definitions
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clock_process :process
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begin
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     clk <= '0';
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     en  <= '0';
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     wait for 10 ns;
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     clk <= '1';
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     en  <= '1';
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     wait for 10 ns;
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end process;
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-- Stimulus process
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stim_proc: process
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begin        
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   -- hold reset state for 100 ns.
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    reset <= '1';
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    wait for 20 ns;    
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    reset <= '0';
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   wait;
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end process;
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-- assertion test
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assert_test: process
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begin
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    wait for 21 ns;
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    if(en = '1') then assert reset /= '1' report "Assertion violation." severity error;end if;
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    if(en = '1') then assert << signal dut.sw : std_logic >> = '1' report "Second Assertion violation." severity error;end if;
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    wait;
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end process;
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end Behavioral;

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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Muhammad Tahir R. wrote:
> but still no success
What do you want to do? What should happen? And what happens instead?


BTW:
>    -- hold reset state for 100 ns.
If you have a comment, it should reflect what happens. Otherwise you'd 
better delete it.

von Muhammad Tahir R. (Company: Self) (tahirsengine)


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Lothar M. wrote:
> Muhammad Tahir R. wrote:
>> but still no success
> What do you want to do? What should happen? And what happens instead?
>
I want to evaluate that assert expression, and when that variable(SW) 
doesn't have the required value(as in assertion) then it should throw an 
error. At the moment, although code is not failing, but this expression 
is also not getting evaluated property, or at all.
Is this right way to check value of SW variable?

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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Muhammad Tahir R. wrote:
> SW variable?
SW ist not a variable. It is a signal. There a huge difference 
between...

> Is this right way to check value of SW variable?
See it that way: a testbench is just a "normal" VHDL entity without any 
ports to somewhere. But in this VHDL module you instantiate components, 
maybe one, maybe several. Those components themself may have other 
components in their entity, and so forth.
And because a testbench is a VHDL module like any other you cannot 
access internal signals just with a '.'

The usual way is to pass signals from the component to the "upper level" 
entity is by means of the port list like the counter, reset and clk...

: Edited by Moderator
von Bernhard K. (bkom)


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Muhammad Tahir R. wrote:
> if(en = '1') then assert << signal dut.sw : std_logic >> = '1'
> report "Second Assertion

works ony with VHDL2008 setting in your simulator - for examples see:
https://www.doulos.com/knowhow/vhdl/vhdl-2008-easier-to-use/
(scroll down)

another example:
https://support.xilinx.com/s/question/0D52E00006hpXtRSAU/correct-syntax-to-reference-a-hierarchical-signal-in-a-vhdl-2008-testbench?language=en_US

: Edited by User

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