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Help - System not functioning as required
von daniel (Guest)

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Hello everyone, I designed a uart successfully.
I initially configured it to enable sending information by a button from 
the FPGA, the information was sent successfully.
After this I designed a timer that will send 24 packets of 8 bits and 
after that it will stop.
Despite this, the system does not stop sending, even though the 
simulation is functioning properly in reality, the UART continues to 
send information.

If you notice - in the category of Synchronize the change to signals is 
limited to 23 and then the system should stop changing the sending 
signals :

  if(counteo <= 23 ) then
        Temp_clk2<=not(Temp_clk2);
        else
        Temp_clk2<='0';
        end if;

1
-- Create Date: 17.05.2022 12:19:31

2
3
library IEEE;

4
use IEEE.STD_LOGIC_1164.ALL;

5
6
7
entity Uart is

8
    Port ( Send : in STD_LOGIC;

9
           clk : in STD_LOGIC;

10
           Data : in std_logic_vector(7 downto 0);

11
           Ready : out STD_LOGIC;

12
           Uart_Tx : out STD_LOGIC);

13
end Uart;

14
15
architecture Behavioral of Uart is

16
constant baud_timer : integer:= 10415;

17
constant bit_index_max : integer:=10;

18
19
type state_type is(Rdy, Load_bit, Send_bit);

20
signal state : state_type :=RDY;

21
signal timer : integer:=0;

22
signal txdata :std_logic_vector(9 downto 0);

23
signal bitIndex: integer range 0 to bit_index_max :=0;

24
signal txbit : std_logic:='1';

25
26
27
begin

28
process(clk)

29
begin

30
if rising_edge(clk) then

31
32
case state is

33
34
when Rdy =>

35
           

36
           if (Send='1') then

37
               txdata <= '1' & data & '0';

38
               state <= Load_bit;

39
           end if;           

40
           timer<= 0;

41
           bitIndex <= 0;

42
           txbit <= '1';

43
           

44
when Load_bit => 

45
            

46
           state <= Send_bit;

47
           bitIndex<= bitIndex +1;

48
           txbit <= txdata(bitIndex);

49
           

50
when seND_BIT =>   

51
        

52
           IF(timer = baud_timer) then

53
           timer <= 0;

54
           if ( bitIndex = bit_index_max) then

55
           state <= Rdy;

56
           else state <= Load_bit;

57
           end if;

58
           else timer <= timer + 1;

59
           end if;

60
end case;

61
end if;

62
end process;

63
Uart_Tx <= txbit;

64
Ready <= '1' when (state = Rdy) else '0';

65
end Behavioral;



1
----------------------------------------------------------------------------------

2
-- Company: 

3
-- Engineer: 

4
-- 

5
-- Create Date: 01.09.2022 01:12:55

6
-- Design Name: 

7
-- Module Name: jghjfk - Behavioral

8
-- Project Name: 

9
-- Target Devices: 

10
-- Tool Versions: 

11
-- Description: 

12
-- 

13
-- Dependencies: 

14
-- 

15
-- Revision:

16
-- Revision 0.01 - File Created

17
-- Additional Comments:

18
-- 

19
----------------------------------------------------------------------------------

20
21
22
library IEEE;

23
use IEEE.STD_LOGIC_1164.ALL;

24
25
-- Uncomment the following library declaration if using

26
-- arithmetic functions with Signed or Unsigned values

27
--use IEEE.NUMERIC_STD.ALL;

28
29
-- Uncomment the following library declaration if instantiating

30
-- any Xilinx leaf cells in this code.

31
--library UNISIM;

32
--use UNISIM.VComponents.all;

33
34
entity infoStorage is

35
    Port ( clk : in STD_LOGIC;

36
           eo : in STD_LOGIC;

37
           dataout : out STD_LOGIC_VECTOR (7 downto 0):="00000000");

38
end infoStorage;

39
40
architecture Behavioral of infoStorage is

41
42
type t_Row_Col is array (0 to 7, 0 to 2) of STD_LOGIC_VECTOR (7 downto 0);

43
44
signal r_Number : t_Row_Col:=

45
( ("01000001","01000010","01000011"),

46
  ("01000100","01000101","01000110"),

47
  ("01000111","01001000","01001001"),

48
  ("01001010","01001011","01001100"),

49
  ("01001101","01001110","01001111"),

50
  ("01010000","01010001","01010010"),

51
  ("01010011","01010100","01010101"),

52
  ("01010110","01010111","01011000")  );

53
signal i : integer range 0 to 7:=0;

54
signal j : integer range 0 to 2:=0;

55
begin

56
57
process(eo,clk)

58
begin

59
60
if(rising_edge (clk)) then 

61
62
    if(eo='1') then 

63
    

64
    dataout<=r_Number(i,j);

65
    

66
    if(j<=1) then 

67
            j<=j+1;

68
            elsif(j=2 and i<=6) then 

69
                j<=0;

70
                i<=i+1;

71
    end if;

72
    

73
    end if ;

74
75
76
end if;

77
78
79
end process;

80
81
end Behavioral;




1
library IEEE;

2
use IEEE.STD_LOGIC_1164.ALL;

3
4
5
6
entity Synchronize is

7
    Port ( clk : in STD_LOGIC; 

8
           clkout : out STD_LOGIC;

9
           clk1 : out STD_LOGIC;

10
           clk2 : out STD_LOGIC;

11
           eo : out STD_LOGIC);

12
end Synchronize;

13
14
architecture Behavioral of Synchronize is

15
signal state1: std_logic:='0';

16
signal state2: std_logic:='0';

17
18
signal count1 : integer range -1001 to 105500001:=-1001;

19
signal count2 : integer range 0 to 103501:=0;

20
signal counteo : integer range 0 to 50:=0;

21
22
23
signal Temp_clk1 :  STD_LOGIC:='0';

24
signal Temp_clk2 :  STD_LOGIC:='0';

25
signal Temp_eo : STD_LOGIC:='1';

26
27
begin

28
process(clk,counteo) begin

29
30
31
32
if( rising_edge(clk) ) then 

33
34
case state1 is 

35
36
    

37
    when '0' =>

38
    

39
    if( count1 = 105499 ) then

40
        count1<=0;

41
        

42
        if(counteo <= 23 ) then 

43
        Temp_clk1<=not(Temp_clk1);

44
        else

45
        Temp_clk1<='0';

46
        end if;

47
        

48
        state1<='1';

49
        

50
    

51
        

52
        

53
    else count1<=count1+1;

54
    end if;

55
    

56
     when others =>  

57
    

58
        if( count1 = 999 ) then

59
        count1<=0;

60
        

61
        

62
        if(counteo <= 23 ) then 

63
        Temp_clk1<=not(Temp_clk1);

64
        else

65
        Temp_clk1<='0';

66
        end if;

67
        

68
        

69
        

70
        

71
        

72
        

73
        counteo<=counteo+1;

74
        

75
        

76
        state1<='0';

77
        

78
        

79
    else count1<=count1+1;

80
    end if;

81
    

82
    

83
    

84
end case;

85
86
case state2 is 

87
88
    

89
    when '0' =>

90
    

91
    if( count2 = 103499 ) then

92
        count2<=0;

93
        

94
        

95
        

96
        if(counteo <= 23 ) then 

97
        Temp_clk2<=not(Temp_clk2);

98
        else

99
        Temp_clk2<='0';

100
        end if;

101
        

102
        

103
        

104
        

105
        state2<='1';

106
        

107
    

108
        

109
        

110
    else count2<=count2+1;

111
    end if;

112
    

113
     when others =>  

114
    

115
        if( count2 = 3999 ) then

116
        count2<=999;

117
        

118
        if(counteo <= 23 ) then 

119
        Temp_clk2<=not(Temp_clk2);

120
        else

121
        Temp_clk2<='0';

122
        end if;

123
        

124
        state2<='0';

125
        

126
        

127
    else count2<=count2+1;

128
    end if;

129
    

130
    

131
    

132
end case;

133
134
135
136
end if;

137
138
-- else 

139
-- Temp_clk2<='0';

140
-- Temp_clk1<='0';

141
---- Temp_eo<='0';

142
-- end if;

143
144
end process;

145
eo<=Temp_eo;

146
clkout<=clk;

147
clk1<=Temp_clk1;

148
clk2<=Temp_clk2;

149
150
end Behavioral;


  


  




  

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    Re: Help - System not functioning as required
  


  

    

      von
      
        FPGA Rettungsdienst (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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Hello,
your urgent request has been noticed.
Please put on the Warnweste and the Dreieck on the street and hold the 
line for additional questions.

Ersthelfers will arrive later this evening.

  


  




  

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        FPGA NOTFALLSEELSORGE (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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So ... it's a pity. you master this complicated language but fail at the 
simplicity of VHDL.

Why do you not even try to format your code in a readable manner? Use 
spaces, use linefeed carrage return and space. They all were invented in 
the analog days centurys ago.

But the biggest problem here is:
You postet three components, but the toplevel or binding component is 
missing. A testbench is missing, too.

So at the moment the possible error may reside in these missing 
components.

Best regards,
-gb-

  


  




  

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        Helpling (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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My guess: counteo overflows and so it is <23 again. Let the simulation 
run a bit longer and also add the relevant signals (FSM states and all 
the different counters, not only the ports) to the waveform.

  


  




  

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        daniel (Guest)
      
      


      
    


    

      
    

    

    

      

      

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1
----------------------------------------------------------------------------------

2
-- Company: 

3
-- Engineer: 

4
-- 

5
-- Create Date: 03.09.2022 18:24:34

6
-- Design Name: 

7
-- Module Name: Top_M_Uart - Behavioral

8
-- Project Name: 

9
-- Target Devices: 

10
-- Tool Versions: 

11
-- Description: 

12
-- 

13
-- Dependencies: 

14
-- 

15
-- Revision:

16
-- Revision 0.01 - File Created

17
-- Additional Comments:

18
-- 

19
----------------------------------------------------------------------------------

20
21
22
library IEEE;

23
use IEEE.STD_LOGIC_1164.ALL;

24
25
-- Uncomment the following library declaration if using

26
-- arithmetic functions with Signed or Unsigned values

27
--use IEEE.NUMERIC_STD.ALL;

28
29
-- Uncomment the following library declaration if instantiating

30
-- any Xilinx leaf cells in this code.

31
--library UNISIM;

32
--use UNISIM.VComponents.all;

33
34
entity Top_M_Uart is

35
    Port ( clk : in STD_LOGIC;

36
           Uart_Tx : out STD_LOGIC;

37
38
           Ready : out STD_LOGIC);

39
end Top_M_Uart;

40
41
architecture Behavioral of Top_M_Uart is

42
43
component Uart is

44
    Port ( Send : in STD_LOGIC;

45
           clk : in STD_LOGIC;

46
           Data : in std_logic_vector(7 downto 0);

47
           Ready : out STD_LOGIC;

48
           Uart_Tx : out STD_LOGIC);

49
end component;

50
51
component infoStorage is

52
    Port ( clk : in STD_LOGIC;

53
           eo : in STD_LOGIC;

54
           dataout : out STD_LOGIC_VECTOR (7 downto 0):="00000000");

55
end component;

56
57
component Synchronize is

58
    Port ( clk : in STD_LOGIC;

59
           

60
           clkout : out STD_LOGIC;

61
           clk1 : out STD_LOGIC;

62
           clk2 : out STD_LOGIC;

63
           eo : out STD_LOGIC);

64
end component;

65
66
67
signal s1,s2,s3,s4,s5 : STD_LOGIC;

68
        

69
signal i1 : STD_LOGIC_VECTOR (7 downto 0);

70
71
begin

72
U1 : Synchronize port map (clk=>s1,clkout=>s2,clk1=>s3,clk2=>s4,eo=>s5);

73
U2 : infoStorage port map (clk=>s4,eo=>s5,dataout=>i1);

74
U3 : Uart        port map (Data=>i1,Send=>s3,clk=>s2,Ready=>Ready,Uart_Tx=>Uart_Tx);

75
76
s1<=clk;

77
end Behavioral;



1
----------------------------------------------------------------------------------

2
-- Company: 

3
-- Engineer: 

4
-- 

5
-- Create Date: 04.09.2022 00:43:51

6
-- Design Name: 

7
-- Module Name: TB_TOPM - Behavioral

8
-- Project Name: 

9
-- Target Devices: 

10
-- Tool Versions: 

11
-- Description: 

12
-- 

13
-- Dependencies: 

14
-- 

15
-- Revision:

16
-- Revision 0.01 - File Created

17
-- Additional Comments:

18
-- 

19
----------------------------------------------------------------------------------

20
21
22
library IEEE;

23
use IEEE.STD_LOGIC_1164.ALL;

24
25
-- Uncomment the following library declaration if using

26
-- arithmetic functions with Signed or Unsigned values

27
--use IEEE.NUMERIC_STD.ALL;

28
29
-- Uncomment the following library declaration if instantiating

30
-- any Xilinx leaf cells in this code.

31
--library UNISIM;

32
--use UNISIM.VComponents.all;

33
34
entity TB_TOPM is

35
--  Port ( );

36
end TB_TOPM;

37
38
architecture Behavioral of TB_TOPM is

39
40
component  Top_M_Uart is

41
    Port ( clk : in STD_LOGIC;

42
           Uart_Tx : out STD_LOGIC;

43
           Ready : out STD_LOGIC);

44
end component;

45
46
signal CLK : std_logic:='0';

47
signal Uart_Tx ,Ready : std_logic;

48
49
begin

50
U1 : Top_M_Uart port map(clk=>clk,Uart_Tx=>Uart_Tx,Ready=>Ready);

51
52
process begin 

53
wait for 5ns;

54
clk<=not(clk);

55
end process;

56
57
end Behavioral;


  


  




  

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SY

  


  




  

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sim

  


  




  

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@ Daniel

Attaching a few screenshots without further ado is … quite rude, 
especially when expecting help

- 1

  


  




  

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Help will arrive soon. The Tatütata is on its way to Unfallstelle.

  


  




  

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Sorry, that's not the intention, I built a system that blocks the 
sending signal to the uart called Synchronize, which provides 2 signals 
- the first is an exchange of the information being sent, and the second 
is a sending enable signal - clk1 The uart receives the signal and sends 
the information as can be seen in the simulations after 24 times the 
signal remains low despite the computer Unlike the simulation, the 
information continues to be sent endlessly

  


  




  

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        daniel (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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FPGA Rettungsdienst wrote:
> Help will arrive soon. The Tatütata is on its way to Unfallstelle

Heiner wrote:
> @ Daniel
>
> Attaching a few screenshots without further ado is … quite rude,
> especially when expecting help
>
> - 1


Sorry, that's not the intention, I built a system that blocks the 
sending signal to the uart called Synchronize, which provides 2 signals 
- the first is an exchange of the information being sent, and the second 
is a sending enable signal - clk1 The uart receives the signal and sends 
the information as can be seen in the simulations after 24 times the 
signal remains low despite the computer Unlike the simulation, the 
information continues to be sent endlessly

  


  




  

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        FPGA Rettungsdienst (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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Well the pictures showing the vivado messages are useless because these 
messages have nothing to do with your problem.

The simulation pictures are useless as well because they only show the 
problem but not the related signals and states inside the problem 
causing components.

Notfallhilfe will simulate for you when it arrives at Unfallstelle.

  


  




  

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        daniel (Guest)
      
      


      
    


    

      
    

    

    

      

      

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FPGA Rettungsdienst wrote:
> Well the pictures showing the vivado messages are useless because
> these
> messages have nothing to do with your problem.
>
> The simulation pictures are useless as well because they only show the
> problem but not the related signals and states inside the problem
> causing components.
>
> Notfallhilfe will simulate for you when it arrives at Unfallstelle.

I didn't quite understand what I should do in such a case...
The simulation shows 100% normality and in reality the received signals 
continue to send the information.

  


  




  

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        FPGA NOTFALLSEELSORGE (Guest)
      
      


      
    


    

      
    

    

    

      

      

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Well,
counteo just counts up. It does not stop counting at 23 or 24. So what 
will happen?

Helpling wrote:
> My guess: counteo overflows and so it is <23 again. Let the
> simulation
> run a bit longer and also add the relevant signals (FSM states and all
> the different counters, not only the ports) to the waveform.

The User was right!

  


  




  

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Helpling wrote:
> My guess: counteo overflows and so it is <23 again. Let the simulation
> run a bit longer

Much longer. This overflow will not happen in feasible simulation time. 
But in Hardware it will happen.

  


  




  

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FPGA NOTFALLSEELSORGE wrote:
> Much longer. This overflow will not happen in feasible simulation time.
> But in Hardware it will happen.

Well, counteo is defined as integer range 0 to 50, so the simulator 
should  give an error in feasible simulation time. In real hardware, the 
overflow will take much longer probably, depends what the synthesizer 
did.

  


  




  

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daniel wrote:
> I didn't quite understand what I should do in such a case...
> The simulation shows 100% normality and in reality the received signals
> continue to send the information.

Look what counteo is doing. It does not stop at 24, but counts and 
counts and counts. So at some point, it will overflow and start from 0 
again.

Solution: Stop counting, when counteo reaches 24.

  


  




  

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Helpling wrote:
> daniel wrote:
>> I didn't quite understand what I should do in such a case...
>> The simulation shows 100% normality and in reality the received signals
>> continue to send the information.
>
> Look what counteo is doing. It does not stop at 24, but counts and
> counts and counts. So at some point, it will overflow and start from 0
> again.
>
> Solution: Stop counting, when counteo reaches 24.


Thank you very much, I looked at it after that I realized what a 
retarded mistake this is.
I'm pretty new and have never been exposed to it having continuity after 
OV.

  


  




  

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daniel wrote:
> I'm pretty new and have never been exposed to it having continuity after
> OV.

Yes, that's a thing we all had to learn.

The more important lesson here is: That was NOT a thing where the 
simulation did not match the synthesized outcome. It was just that you 
observed some microseconds in simulation and observed some seconds on 
real hardware, where the "erroneous" behavior occured after the time 
slot you simulated.

So the conclusion "In sim it is working, on hardware not" was not 
correct. You always have to interpolate what will happen, when the 
design runs longer than the simulated time and keep in mind that 
hardware runs much faster than simulation.

  


  




  

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