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Forum: FPGA, VHDL & Verilog How to test multiple instances with test file


von AmoonJ (Guest)


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I have a set of test vectors saved in a csv file and formatted as 
follows:
1
0010,1000,1010
2
1110,0101,0001
3
1001,0001,0000
These are randomly generated and can be of any arbitrary length or 
number. Here the number is 3 (3 vectors per row) and length is 4 (4 bits 
for each vector).

I wanted to read these vectors in verilog and apply them to an array of 
instastiated modules. In other words, 0010 will be applied to the first 
instance, 1010 to the third instance. Next apply 1110 to first instance, 
0001 to the third and so on.

We have three latches (Lat Module) and we are generating 3 instances of 
it in Lat_array module. I want the operation be like: first indexed 
instance gets the first 4 bits, second instance gets the second set of 
four bits and the final instance gets the last four bits in the row. All 
of them get the 4bits at the same time and output at the same. After 
that, the data in the next row is applied in the same order as another 
input test vectors. The desired vs actual waveforms are attached.

I tried the following code, I could test a single module, but I dont 
know how to test several instances using the test vectors above. Could 
you please guide me where I doing wrong and how to implement this?

Top level module:
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module Lat_array #(parameter number =3, parameter length = 4)(ins, clks, resets,outs);
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input [length- 1:0] ins;
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input clks, resets;
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output [length-1:0] outs;
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generate
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 genvar i;
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 for (i=0; i<number; i=i+1) begin
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   Lat lat(
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     .clk(clks)
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    ,.reset(resets)
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    ,.in(ins)
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    ,.out(outs)
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    );
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 end
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endgenerate
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endmodule
The Lat module:
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module Lat #(parameter length = 4)(in, clk, reset,out);
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input [length- 1:0] in;
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input clk, reset;
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output [length-1:0] out;
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reg [length-1:0] res;
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always @ (posedge clk) begin
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if (!reset)
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    res <= 0;
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else
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    res <= in;
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end
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assign out = res;
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endmodule
Testbench:
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`timescale 1ns/1ps
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module tb;
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parameter number = 3;
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parameter length = 4;
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reg [length-1:0] in;
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reg clk, reset;
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wire [length-1:0] out;
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Lat_array #(.number(number), .length(length)) lat_insts (.ins(in), .clks(clk), .resets(reset), .outs(out));
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initial begin
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reset <=0;
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clk <=0;
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end
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always @(clk) #100 clk <= ~clk;
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reg [length-1:0] temp;
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reg [length- 1:0] test_in [(3*number)-1:0];
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integer f, k;
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initial begin
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#500 reset <= 1;
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     in <= 0;
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f = $fopen("test.csv", "r");
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 for (integer i = 0; i < 3; i = i + 1)
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  //while(! $feof(f))
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  begin
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        for(integer j = 0; j < number; j = j + 1)
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        begin
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            k = $fscanf(f,"%b,",temp);
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            $display("%b", temp);
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            test_in[j] = temp;
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        end
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        #10; in = test_in[i-1];
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  end
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  #200 reset <=0;
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  $monitor("in=%b, out=%b", in, out);
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#1000 $finish;
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end
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endmodule

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