I have a set of test vectors saved in a csv file and formatted as
follows:
1
0010,1000,1010
2
1110,0101,0001
3
1001,0001,0000
These are randomly generated and can be of any arbitrary length or
number. Here the number is 3 (3 vectors per row) and length is 4 (4 bits
for each vector).
I wanted to read these vectors in verilog and apply them to an array of
instastiated modules. In other words, 0010 will be applied to the first
instance, 1010 to the third instance. Next apply 1110 to first instance,
0001 to the third and so on.
We have three latches (Lat Module) and we are generating 3 instances of
it in Lat_array module. I want the operation be like: first indexed
instance gets the first 4 bits, second instance gets the second set of
four bits and the final instance gets the last four bits in the row. All
of them get the 4bits at the same time and output at the same. After
that, the data in the next row is applied in the same order as another
input test vectors. The desired vs actual waveforms are attached.
I tried the following code, I could test a single module, but I dont
know how to test several instances using the test vectors above. Could
you please guide me where I doing wrong and how to implement this?
Top level module: