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Forum: FPGA, VHDL & Verilog


Programmable logic


Subject Author Replies Last post
sticky FPGA development resources Andreas S. 15
IP CORES to vhdl by xilinx ISE Elico C. 4
LOW COST BOARDS FOR Vivado Elico C. 3
Write a very simple controller for a flash memory in a IC board Pinellia Chen 0
test bench for digitAL PI controller Rock B. 0
Hardware Target shutdown problem in nexys 4 ddr Lakshita J. 6
PCI verilog code with all modules present niranjan mamadapur 2
PI loop filter in Verilog Rock B. 3
Artix-7 SPI (x4) bitstream does not work for SelectMAP (x16) St. D. 2
Generic Adder in VHDL Martin 7
VIVADO vs ISE elico 2
Deriving different clock signals from a system clock - frequency division & flags Sushma K S 2
LUT utilization is 121 % Lakshita J. 11
Synthesis doesn't match simulation Kyle Gacek 4
External oscillator on my LatticeXP2 Brevia2 Neoz 5
Phase detector in Xilinx Rock B. 23
Combinatorial logic Julian Mortimer 0
Count number of more than 4 consecutive zeros Usman Ashraf 4
4-bit counter simulation problem Paolo 2
simple syntax error near clk Rock B. 11
how to program mojo plus board with ise design Pouya Nosratkhah 1
Implement FIR filter in verilog using FDA tool Usman Ashraf 5
Help in simulating ALU with register file Fadi CPP 0
how to scale output of butterfly unit radix 2 for further stages Pravesh Rathee 2
VHDL code HELP PLZ CARL 1
RS232 from http://www.lothar-miller.de. SparkyT 1
An array of std_logic_vector driven by two processes. Pablo Picasso 2
Quartus II connect bus to 2D array-input of block C17 3
verbose output from quartus Quentin 0
the verilog code occupies the hole resources Alireza Shavakandi 3
VGA controller-Verilog sinhton 9
Zero-overhead blocking AXI4-stream function Julian Mortimer 0
Systolic Array Dayana Saiful 20
Is this nonesense? Julian Mortimer 3
Need help in code Gombo Khorloo 3
Help in vhdl project Bozidar Kelava 7
PSO based fir filter design and functional verification in fpga Bharat Lal106 3
Skipped part of design Op Op 2
Tocken bucket based on FIFO Melisa Čehajić 0
checking different channels Richard Turner 7
SNAKE GAME VHDL Ya Yo 4
Input Capture using FPGA Michael Javier 1
Help with VHDL Jaden 2
portmap problem, implementing the smallest part Rock B. 1
Snakegame VHDL sinhton 3
VHDL code for Rnon Snon (NAND) Flip flop Martin 21
Multiplication fixed floating-point Martin 16
Cortex-fabric communication Oscar Garcia 0
Counter that goes up to 9 and down Jason Jellos 14
Fullbuffer for local image operations Tom Schlogel 0
if error on sequence detector Rock B. 4
Query regarding 32bits ALU design NIDHI KHANNA 1