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Forum: FPGA, VHDL & Verilog verbose output from quartus


Author: Quentin (Guest)
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Hi folks!

I usually start my FPGA builds from Makefile.
The Xilinx toolchain (xst) gives a lot of information about the 
synthezied design units:
Analyzing hierarchy for entity <transmitter> in library <work> (architecture <behavioral>) with generics.
  FREQ = 3780923
  RATE = 115200
Synthesizing Unit <transmitter>.
    Related source file is "x:.../transmitter.vhd".
    Found finite state machine <FSM_1> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 9                                              |
    | Inputs             | 6                                              |
    | Outputs            | 5                                              |
    | Clock              | clock                     (rising_edge)        |
    | Reset              | reset                     (positive)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <busy>.
    Found 4-bit up counter for signal <bits>.
    Found 8-bit register for signal <byte>.
    Found 1-bit register for signal <byteDone>.
    Found 3-bit register for signal <bytes>.
    Found 3-bit adder for signal <bytes$addsub0000> created at line 135.
    Found 6-bit up counter for signal <counter>.
    Found 32-bit register for signal <dataBuffer>.
    Found 1-bit register for signal <disabled>.
    Found 4-bit register for signal <disabledBuffer>.
    Found 1-bit register for signal <paused>.
    Found 10-bit register for signal <txBuffer>.
    Found 1-bit register for signal <writeByte>.
    Summary:
  inferred   1 Finite State Machine(s).
  inferred   2 Counter(s).
  inferred  62 D-type flip-flop(s).
  inferred   1 Adder/Subtractor(s).
Unit <transmitter> synthesized.

From the Altera toolchain (Quartus) I only get a poor:
Info (12021): Found 2 design units, including 1 entities, in source file .../T80/T80s.vhd
    Info (12022): Found design unit 1: T80s-rtl
    Info (12023): Found entity 1: T80s

I look in "Quartus II Scripting Reference Manual - Altera" and "AN 309: 
Command-Line Scripting in the Quartus II Software" but found no suitable 
switch.

Does anybody know a way to get a more verbose output for the synthesis 
results?

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