Eliahu C. wrote:
> In case of doing a design based on IP cores with XILINX ISE is it
> possible to transform the IP cores to VHDL by the ISE tool ?
Third party IP cores usually are provided as a unreadable binary
netlist. You only get a wrapper to connect the ports of the IP core to
your design. And even when you could transform it to VHDL does not mean
that you could implement it again the very same way to get a running
> is it possible
To keep things short: No.
Or can you transform a scrambled egg back to its original form?