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Forum: FPGA, VHDL & Verilog IP CORES to vhdl by xilinx ISE


Author: Elico C. (Company: WS) (elico)
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In case of doing a design based on IP cores with XILINX ISE is it 
possible to transform the IP cores to VHDL by the ISE tool ?

Thanks
elico

Author: Lothar M. (lkmiller) (Moderator)
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Eliahu C. wrote:
> In case of doing a design based on IP cores with XILINX ISE is it
> possible to transform the IP cores to VHDL by the ISE tool ?
Third party IP cores usually are provided as a unreadable binary 
netlist. You only get a wrapper to connect the ports of the IP core to 
your design. And even when you could transform it to VHDL does not mean 
that you could implement it again the very same way to get a running 
design again...

> is it possible
To keep things short: No.
Or can you transform a scrambled egg back to its original form?

Author: Elico C. (Company: WS) (elico)
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And if the IP cores come from the XILINX software itself ?

Elico

Author: Duke Scarring (Guest)
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Eliahu C. wrote:
> And if the IP cores come from the XILINX software itself ?
Even then.

Particulare cores are readable (mig), but others not.

Duke

Author: Elico C. (Company: WS) (elico)
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thanks

Elico

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