Forum: FPGA, VHDL & Verilog PI loop filter in Verilog

von Rock B. (rocko445)

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Hello, the attached photo is taken from the attached article,

The line bellow doesnt resemble any line on the right side, how it 
describes the formula on the right?


: Edited by User
von Kyle G. (kyle_g)

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From what I understand about PID controllers is that the integral 
portion is just an accumulator. Which is why its integral = integral + 
FILT_I. Each time it adds the current value to the 

The formulas on the right are for the analog filter in the article, 
which is made with an op amp. I'm not sure you're going to find a 
correlation between the two.

Just my two cents.

von Rock B. (rocko445)

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Hello, There are two variables, integral and proportional when clk=1 
integral decreases ,when clk=0 then it decreases.

proportional toggles from negative to positive with the FILT amplitude.

and both of them goes into vtcl with is the factor controlling the 
period of the VCO.

how this logic represnt PID loop filter?


: Edited by User


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