EmbDev.net

Forum: FPGA, VHDL & Verilog PSO based fir filter design and functional verification in fpga


PSO based fir filter design and functional verification in fpga
von Bharat L. (Company: IU) (bharat106)

Rate this post
• ▲ useful
▼ not useful 
Hello friends. I want to design FIR Low pass filter using PSO algorithm 
and it functional verification in FPGA. can any one share VHDL code for 
Particle swarm optimization (PSO) based FIR filter?

Report post Edit Move Thread sperren Anmeldepflicht DEaktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
Re: PSO based fir filter design and functional verification in fpga
von mikro (Guest)

Rate this post
• ▲ useful
▼ not useful 
How about doing it on your own?

Report post Edit Delete Quote selected text Reply Reply with quote
Watch this topic | Disable multi-page view
Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
No account? Register here.