Forum: FPGA, VHDL & Verilog PSO based fir filter design and functional verification in fpga

von Bharat L. (Company: IU) (bharat106)

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Hello friends. I want to design FIR Low pass filter using PSO algorithm 
and it functional verification in FPGA. can any one share VHDL code for 
Particle swarm optimization (PSO) based FIR filter?

von mikro (Guest)

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How about doing it on your own?


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