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Forum: FPGA, VHDL & Verilog Help with VHDL


von Jaden (Guest)


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Hello,

I'm quite new to VHDL and trying to create a simple UART transmission in 
VHDL code.

This is my code:
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entity UART is 
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  port ( din  : in bit_vector( 7 downto 0) ;
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       send : in std_logic ;
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       tx  : out bit ) ;
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end UART;
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architecture arc_UART of UART is
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begin
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  process
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    constant bit_time : time := 8680 ns ;  -- 1/115200 [baud]
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  begin
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    tx <= '1' ;                -- idle state  
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    wait until falling_edge(send) ;       -- wait until send
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    tx <= '0' ; wait for bit_time ;       -- start bit
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    for i in 0 to 7 loop
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      tx <= din(i) ; wait for bit_time ; -- send 8 data bits
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    end loop ;
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    tx <= '1' ; wait for bit_time ;       -- stop bit
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  end process;
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end arc_UART;

But the problem is that when I run a Model-sim simulation, it doesn't 
work as expected.


What could be the problem here?

Thank you

von Lothar M. (lkmiller) (Moderator)


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Jaden wrote:
> it doesn't work as expected.
What do you expect and what happens instead?

> What could be the problem here?
You know that "wait for" is not synthesizable on real hardware like a 
FPGA?

von U.G. L. (dlchnr)


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I suppose you need something like a loadable shift register plus a 
baudrate generator (clock divider),
which generates the shift clock (sclk) from your system clock.
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ShiftRegister : process                                                                         
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begin                                                                                        
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  wait until rising_edge(sclk);                                                          
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  if (load = '1') then
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    sr(7 downto 0) <= din(7 downto 0);
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    tx <= '0';
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  else                                                                 
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    sr(6 downto 0) <= sr(7 downto 1);
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    sr(7) <= '1';                                                  
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    tx <= sr(0);                                                                          
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  end if;                                                                                    
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end process;

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