Help with VHDL

Jaden Guest #5259361
Rate this post
• ▲ useful
▼ not useful 
Hello,

I'm quite new to VHDL and trying to create a simple UART transmission in 
VHDL code.

This is my code:
1
entity UART is 

2
  port ( din  : in bit_vector( 7 downto 0) ;

3
       send : in std_logic ;

4
       tx  : out bit ) ;

5
end UART;

6


7
architecture arc_UART of UART is

8
begin

9
  process

10
    constant bit_time : time := 8680 ns ;  -- 1/115200 [baud]

11
  begin

12
    tx <= '1' ;                -- idle state  

13
    wait until falling_edge(send) ;       -- wait until send

14
    tx <= '0' ; wait for bit_time ;       -- start bit

15
    for i in 0 to 7 loop

16
      tx <= din(i) ; wait for bit_time ; -- send 8 data bits

17
    end loop ;

18
    tx <= '1' ; wait for bit_time ;       -- stop bit

19
  end process;

20
end arc_UART;


But the problem is that when I run a Model-sim simulation, it doesn't 
work as expected.


What could be the problem here?

Thank you
Reply Quote Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Report post
U.G. L. #5259551
Rate this post
• ▲ useful
▼ not useful 
I suppose you need something like a loadable shift register plus a 
baudrate generator (clock divider),
which generates the shift clock (sclk) from your system clock.

1
ShiftRegister : process                                                                         

2
begin                                                                                        

3
  wait until rising_edge(sclk);                                                          

4
  if (load = '1') then

5
    sr(7 downto 0) <= din(7 downto 0);

6
    tx <= '0';

7
  else                                                                 

8
    sr(6 downto 0) <= sr(7 downto 1);

9
    sr(7) <= '1';                                                  

10
    tx <= sr(0);                                                                          

11
  end if;                                                                                    

12
end process;
Reply Quote Edit Delete Report post
Watch this topic

Reply

Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.

Formatting
  • [c]C-Code[/c]
  • [vhdl]VHDL-Code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]
  • [[Title]] – link to an article
  • Link to another post: right-click its post ID (#8078628), copy the address, paste it into the text

More about formatting

Post long source code as an attachment, not in the text.

Your name and e-mail address

Already registered? Log in

Not shown to anyone. We send you a link; your post appears once you confirm it there.

By submitting you create a free account and accept the terms of use.