Forum: FPGA, VHDL & Verilog Help with VHDL

von Jaden (Guest)

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I'm quite new to VHDL and trying to create a simple UART transmission in 
VHDL code.

This is my code:
entity UART is 
  port ( din  : in bit_vector( 7 downto 0) ;
       send : in std_logic ;
       tx  : out bit ) ;
end UART;

architecture arc_UART of UART is
    constant bit_time : time := 8680 ns ;  -- 1/115200 [baud]
    tx <= '1' ;                -- idle state  
    wait until falling_edge(send) ;       -- wait until send
    tx <= '0' ; wait for bit_time ;       -- start bit
    for i in 0 to 7 loop
      tx <= din(i) ; wait for bit_time ; -- send 8 data bits
    end loop ;
    tx <= '1' ; wait for bit_time ;       -- stop bit
  end process;
end arc_UART;

But the problem is that when I run a Model-sim simulation, it doesn't 
work as expected.

What could be the problem here?

Thank you

von Lothar M. (lkmiller) (Moderator)

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Jaden wrote:
> it doesn't work as expected.
What do you expect and what happens instead?

> What could be the problem here?
You know that "wait for" is not synthesizable on real hardware like a 

von U.G. L. (dlchnr)

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I suppose you need something like a loadable shift register plus a 
baudrate generator (clock divider),
which generates the shift clock (sclk) from your system clock.
ShiftRegister : process                                                                         
  wait until rising_edge(sclk);                                                          
  if (load = '1') then
    sr(7 downto 0) <= din(7 downto 0);
    tx <= '0';
    sr(6 downto 0) <= sr(7 downto 1);
    sr(7) <= '1';                                                  
    tx <= sr(0);                                                                          
  end if;                                                                                    
end process;


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