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Forum: FPGA, VHDL & Verilog Multiplication fixed floating-point


Author: Martin (Guest)
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Hello there, i got there another homework as final of semester.

Entering: Create and test the parameterizable implementation of the 
integer multiplication algorithm in a fixed floating point. The 
parameter must be the number of input bits
operands.

They give us something there as hints:
Let A [n-1: 0],
B [n-1: 0],
Q [n-1: 0],
C [1] and PC are registers.

PC serves as a cycle counter.
Let's put C#Q#A on the label linking registers.

Algorithm of integer multiplication:
BEGIN
C#Q :=0 || PC:=n
WHILE(PC>0)
IF A(0) = 1 THEN
C#Q := Q+B
ENDIF
C#Q#A :=0 # SR1(C#Q#A)||
PC := PC - 1
END
END

After that we got Steps of integer multiplication in binary.
How to start with it? Some solutions? I am so newbie at that 
problematics of VHDL codes, scripts.

Author: Lothar M. (lkmiller) (Moderator)
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Martin wrote:
> a fixed floating point.
I do not understand what this may be.
I know either "floating point" numbers or "fixed point" numbers.
But a "fixed floting point number" is such a thing like a "flying 
submarine".
A "fixed point" number/integer is looking like a normal number/integer. 
Only you add a mental position to it which represets a point. The 
whole behaviour of the integer always stays the same.
Its a little bit like having a current of 3456 mA in a wire. That is the 
very same current like 3.456 A. It is the same current. Just divided by 
1000 and therefore getting a point.

So the integer (the current) itself doesn't even "know" that it has a 
pinot in it. You can handle it (add, sub, mul...) like a "normal" 
integer. Only you must keep an eye on the position of the point:
lets multiply two numbers: 100 * 100 = 10000
When those numbers 100 would be 2.1 fixed point numbers they would 
represent 10.0 and the result of the multiplication 10000 must will have 
the format 4.2, so you must position the point in a way you have 2 
fractional digits: 100.00

> Algorithm of integer multiplication:
Thats the usual multiplication like you do it with a pencil on a sheeet 
of paper.

> Q [n-1: 0]
That is wrong. It must be Q[2n-1 : 0] because the result of a 
multiplication is as wide as the sum of both inputs width!
Its easy to see: let n be 8, so we get an integer ranging from -128 to 
128. So we can easily calculate 100*100 = 10000. Fairly easy to see, 
that this result does not fit into -128 to 127...

> How to start with it?
Write a code for multiplying two unsigned integers without any point. 
Wrap that code with a sign-handler. Preform the multiplication of the 
fixed integer number like it would be a "normal" integer. Align the 
result to the output register in a way that the "point" (which is only a 
mental point) is at the correct position. Thats all.

You will need some sheets of paper and a few hours of thougts to get 
it...

: Edited by Moderator
Author: Martin (Guest)
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It isnt working.. I have tried many tutorials and no one was good. Do 
you have some example of that for projects like that is? Thanks

Author: Martin (Guest)
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I have read something on forum, where i found this code for 
multiplication..
  library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity MultExample is
Port (C : OUT unsigned (31 downto 0));
end MultExample;

architecture Behavioral of MultExample is

constant A: integer:= 4;
constant B: integer:= 2;

begin

C <=TO_UNSIGNED(A*B,32);

end Behavioral;
There one advanced user told that, C is still 32-bit as result of 
multiplication of 2 integers. But how to apply something like that to my 
problem? Thanks

Author: Martin (Guest)
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n-1 : 0 says that from number to downto 0?

Author: Lothar M. (lkmiller) (Moderator)
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That means you have n bits wide vectors.
In VHDL you would write (n-1 downto 0).

Martin wrote:
> There one advanced user told that, C is still 32-bit as result of
> multiplication of 2 integers. But how to apply something like that to my
> problem?
It's a thoroughly correct but in your case absolutely useless 
information.
Maybe you asked the wrong question...

Martin wrote:
> It isnt working.. I
What is "it"?

Author: Martin (Guest)
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I must user generic but it cannot compile. Does you have sketch of 
something where is  multiplication with generic form n downto 0?

Author: Martin (Guest)
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I must send it tomorrow to my teacher and i havent nothing.

Author: Lothar M. (lkmiller) (Moderator)
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Try this:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity MultExample is
Generic ( n  : natural := 16);
Port (a,b : in std_logic_vector(n-1 downto 0),
          c.  : out std_logic_vector(2*n-1 downto 0));
end MultExample;

architecture Behavioral of MultExample is
begin

    c <= std_logic_vector(unsigned(a)*unsigned(b));

end Behavioral;

Author: Martin (Guest)
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You had one error in your code, i fixed it. Code is working, Waveform 
simulation too.
How can i put my A[n-1 : 0] to code? Only put that to Port like:
A : in std_logic_vector(n-1 downto 0);
Nothing else?
How about testing with Altera..I need testbench right? Some advices to 
vhdl code at entity?
I don't have so much time for realization.

Author: Martin (Guest)
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How to set C as 1 it will be input i think...
Can you tell me? Thanks a lot! Compilation is unsucessful.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity MultExample is
Generic ( n  : natural := 16);
Port (A,B,Q : in std_logic_vector(n-1 downto 0);        
        C  : std_logic:='1';
      PC : in std_logic_vector(n-1 downto 0));
       
end MultExample;

architecture Behavioral of MultExample is
begin

  
C#Q :=0 || PC:=n
WHILE(PC>0)
IF A(0) = 1 THEN
C#Q := Q+B
ENDIF
C#Q#A :=0 # SR1(C#Q#A)||
PC := PC - 1
END
END

end Behavioral;
Is alghoritm ok in Behavioral? Or it must be in process or something 
like that? Thanks a lot for help.

Author: Lothar M. (lkmiller) (Moderator)
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Martin wrote:
> Is alghoritm ok in Behavioral?
It's a pseudo language. The synthesizer will not understand it. It will 
produce lots of errors.

> Port (A,B,Q : in std_logic_vector(n-1 downto 0);
Why Q?

My best hint ist to discuss this little piece of homework with one of 
your classmates! I can't see no progress here with that topic. We are 
discussing about things on a level similar to 1+1 in arithmetics...

: Edited by Moderator
Author: Martin (Guest)
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Pseudo language? How now use it? Must i remake it to VHDL format? Or 
where attach it? No one from my classmates got similar homework. What is 
Q?
I got homework: A, B, Q, C, PC are registers, PC is cycle counter. 
Please help me. I can not do that alone.

Author: Lothar M. (lkmiller) (Moderator)
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Martin wrote:
> Must i remake it to VHDL format?
First you must understand the algorithm in those lines. Then you can 
convert them to VHDL.

The inputs are two operands as vectors and the output is one vector of 
(curiously) the same length.

The PC (name it progress counter) and the C (name it carry) are only 
local signals.

Indeed the text of that exercise is wrong (or at least misleading), 
because due to the fact that a multiplication is thoroughly 
combinatorial there are no registers needed to get the result.

Author: Martin (Guest)
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I don't know how to format pseudo code to VHDL code. Yes, i understand 
to that there are 2 inputs A, B. Q is output of same lenght, because it 
got parameter n-1 downto 0.
Understand. But i don't have experiences to make code to VHDL script 
from that pseudo code. Can you help me little bit with some VHDL demo 
with my variables please?

Author: Martin (Guest)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity MultExample is
Generic ( n  : natural := 16);
Port (A,B,Q : in std_logic_vector(n-1 downto 0);        
        C  : std_logic:='1';
      PC : in std_logic_vector(n-1 downto 0));
       
end MultExample;

architecture Behavioral of MultExample is

BEGIN
  C#Q := 0 || PC := n
  WHILE (PC > 0)
    IF A(0) = 1 THEN
      C#Q := Q + B
    END IF
    C#Q#A := 0 #SR1(C#Q#A) ||
      PC := PC - 1
    END  
  END
end Behavioral;

Can you edit it please?

Author: Martin (Guest)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity MultExample is
Generic ( n  : natural := 16);
Port (A,B : in std_logic_vector(n-1 downto 0);        
      C  : std_logic:='1';
      Q : out std_logic_vector(n-1 downto 0);
      PC : in std_logic_vector(n-1 downto 0));
       
end MultExample;

architecture Behavioral of MultExample is

BEGIN
  Q <= std_logic_vector(unsigned(A) * unsigned(B));
end architecture Behavioral;
How about something like that? Can you help me?

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