Hello,
as I just started learning VHDL I still have a number of problems 
getting things running.
I would like to write a generic adder which adds to input values bit by 
bit.
In order to realize the generic functionality of the adder three 
std_logic_vectors were introduced which contain the input and the output 
(when the input was processed).

To check, if everything works correctly, I wrote a test bench. And 
that's where the problems start. When running the syntax check I get an 
error message telling me that n is not declared (in the section where 
the signals are declared).

VHDL code of the test bench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY adder_tb IS
END adder_tb;

architecture behaviour of adder_tb is
  component adder
    generic(n : integer := 4);
    port(
      x : IN std_logic_vector(n-1 downto 0);
      y : IN std_logic_vector(n-1 downto 0);
      sum : OUT std_logic_vector(n-1 downto 0 );
      cout : OUT std_logic
    ); 
  end component;

  signal x_sig, y_sig, sum_sig : std_logic_vector(n-1 downto 0);
  signal cout_sig : std_logic := '0';
  
begin
    uut: adder PORT MAP (
          x => x_sig,
          y => y_sig,
          sum => sum_sig,
          cout => cout_sig
        );
end behaviour;

Does anybody see the problem? Thanks very much in advace!!!!

The problem is in the line

signal x_sig, y_sig, sum_sig : std_logic_vector(n-1 downto 0);

n is not declared at this point. You have to add it as a generic or 
local in adder_tb.

You might think that the line

    generic(n : integer := 4);

declares n to be 4. However, this declaration is local to the component 
'adder' and does not extend to the signal declaration for x_sig and the 
like.

Hi,
thanks for the quick reply. Unfortunately it didn't quite help. The 
syntax check tells me there is a syntax error in the line where I 
declare n and that n is still not declared in the line below. Seems 
strange to me...

Hi,
thanks a lot. It works!!!