Hello,
as I just started learning VHDL I still have a number of problems
getting things running.
I would like to write a generic adder which adds to input values bit by
bit.
In order to realize the generic functionality of the adder three
std_logic_vectors were introduced which contain the input and the output
(when the input was processed).
To check, if everything works correctly, I wrote a test bench. And
that's where the problems start. When running the syntax check I get an
error message telling me that n is not declared (in the section where
the signals are declared).
VHDL code of the test bench:
1 | LIBRARY ieee;
|
2 | USE ieee.std_logic_1164.ALL;
|
3 | USE ieee.std_logic_unsigned.all;
|
4 | USE ieee.numeric_std.ALL;
|
5 |
|
6 | ENTITY adder_tb IS
|
7 | END adder_tb;
|
8 |
|
9 | architecture behaviour of adder_tb is
|
10 | component adder
|
11 | generic(n : integer := 4);
|
12 | port(
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13 | x : IN std_logic_vector(n-1 downto 0);
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14 | y : IN std_logic_vector(n-1 downto 0);
|
15 | sum : OUT std_logic_vector(n-1 downto 0 );
|
16 | cout : OUT std_logic
|
17 | );
|
18 | end component;
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19 |
|
20 | signal x_sig, y_sig, sum_sig : std_logic_vector(n-1 downto 0);
|
21 | signal cout_sig : std_logic := '0';
|
22 |
|
23 | begin
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24 | uut: adder PORT MAP (
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25 | x => x_sig,
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26 | y => y_sig,
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27 | sum => sum_sig,
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28 | cout => cout_sig
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29 | );
|
30 | end behaviour;
|
Does anybody see the problem? Thanks very much in advace!!!!
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