Generic Adder in VHDL

Martin Guest #1272290
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Hello,
as I just started learning VHDL I still have a number of problems 
getting things running.
I would like to write a generic adder which adds to input values bit by 
bit.
In order to realize the generic functionality of the adder three 
std_logic_vectors were introduced which contain the input and the output 
(when the input was processed).

To check, if everything works correctly, I wrote a test bench. And 
that's where the problems start. When running the syntax check I get an 
error message telling me that n is not declared (in the section where 
the signals are declared).

VHDL code of the test bench:

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LIBRARY ieee;

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USE ieee.std_logic_1164.ALL;

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USE ieee.std_logic_unsigned.all;

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USE ieee.numeric_std.ALL;

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ENTITY adder_tb IS

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END adder_tb;

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architecture behaviour of adder_tb is

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  component adder

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    generic(n : integer := 4);

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    port(

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      x : IN std_logic_vector(n-1 downto 0);

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      y : IN std_logic_vector(n-1 downto 0);

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      sum : OUT std_logic_vector(n-1 downto 0 );

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      cout : OUT std_logic

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    ); 

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  end component;

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  signal x_sig, y_sig, sum_sig : std_logic_vector(n-1 downto 0);

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  signal cout_sig : std_logic := '0';

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begin

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    uut: adder PORT MAP (

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          x => x_sig,

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          y => y_sig,

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          sum => sum_sig,

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          cout => cout_sig

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        );

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end behaviour;



Does anybody see the problem? Thanks very much in advace!!!!
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Morin Guest #1272353
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The problem is in the line
1
signal x_sig, y_sig, sum_sig : std_logic_vector(n-1 downto 0);


n is not declared at this point. You have to add it as a generic or 
local in adder_tb.

You might think that the line
1
    generic(n : integer := 4);

declares n to be 4. However, this declaration is local to the component 
'adder' and does not extend to the signal declaration for x_sig and the 
like.
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Hartmut S. #1272355
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Hi Martin,

the error arises at the line

signal x_sig, y_sig, sum_sig : std_logic_vector(n-1 downto 0);

thats because your architecture doesn't know "n". "n" is defined in the 
component part only and will be forwarded to "adder" only. So add a 
"signal n : integer := 4;" before the signal definitions in the 
architecture and it will run.
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Martin Guest #1272481
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Hi,
thanks for the quick reply. Unfortunately it didn't quite help. The 
syntax check tells me there is a syntax error in the line where I 
declare n and that n is still not declared in the line below. Seems 
strange to me...
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Lothar M. Moderator (Company: Titel) #5326647
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CHIRAZ wrote:
> Hi, I would like to implement a generic adder in VHDL  for integers does
> any body can help me thank you.
What is the problem with your adder?
How did you find the problem?
What do you expect and wht happens instead?

Here "start" is not needed in teh sensitivity list:
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PROCESS (clk,reset,start)


Why do you have a clock in your design?
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   ELSIF(clk'event and clk='1') then

A adder is a completely logic device. There is no register needed.
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