Neoz wrote:

> But all other I/Os are parasitized by this clock.

What du you mean with "parasitized"?

>
> I checked the wiring and it seems good. The clock works normally.
>
> My question : Is there a special I/O made to be a clock ? The actual
> oscillator of 50 Mhz is on pin 21 of the FPGA. I put mine on pin 106.
>

Pin 106 is a GND Pin. So you missed something while checking.

There are actually pins which have a special funktion for clock input, 
you should use one of them.
On the LFXP2-5E-5TN144C these are: 21,28,56,61,78,88,116,120

But why don't you use a PLL (the LFXP2-5E has two) do create a 12 MHz 
clock from the onboard 50 MHz oscillator?

> What du you mean with "parasitized"?

There is lot of noise on input and output signals.

> Pin 106 is a GND Pin. So you missed something while checking.
>
> There are actually pins which have a special funktion for clock input,
> you should use one of them.
> On the LFXP2-5E-5TN144C these are: 21,28,56,61,78,88,116,120

Yep sorry, it is on pin 116, not 106. So this is ok for the input.

> But why don't you use a PLL (the LFXP2-5E has two) do create a 12 MHz
> clock from the onboard 50 MHz oscillator?

I never tried to use this so I'll see how it works ;)


Thanks a lot!

I attached a screenshot of my signals.

In blue : the good signal without noise.
In red : the signal I have with this new development board.

Neoz wrote:
> I attached a screenshot of my signals.
>
> In blue : the good signal without noise.
> In red : the signal I have with this new development board.

This looks bad, but i doubt it is caused by the development board 
itself. (unless it is already damaged)

Check the Vccio (3.3V) with the scope. If you power your external 
hardware from the development board, you possible may draw to much 
current. Also keep in mind the limitations for USB power.

Recheck your wiring again, with emphasis on good ground connections. A 
bad ground connection can cause all kinds of weird behavior.

Check if the signals from the FPGA are ok while nothing extrenal is 
connected.

Hi, I am also new to MACHXO2 FPGAs, IMHO CLK0, CLK1, and so on are 
Lattice Diamond primitives. This worked for me:

1

module main

2

(

3

  input CLK0,

4

  output reg led,

5

        output enable_osc

6

);  

7

8

  assign enable_osc = 1'b1;

9

10

11

  always @( posedge CLK0 ) // or CLK1, CLK2, etc...

12

  begin

13

    led <= ! led;

14

  end

15

16

endmodule

Notice that the external oscillator has a enable input that is connected 
to pin 32 of the FPGA through a zero ohm resistor, you should either cut 
that resistor(the oscillator have a pull-up resistor inside), or output 
a high level to this pin.