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Forum: FPGA, VHDL & Verilog Count number of more than 4 consecutive zeros


Author: Usman Ashraf (Company: LUMS) (usmanashraf678)
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Dear Members,
I am writing a verilog module that can count the number of zeros in my 
input data flowing in. Each input sample is 10 bit. And I only want to 
count zeros if 4 consecutive samples are zero.

For example, for the input samples:
[74 0 0 0 0 0 54 23 0 0 0 84 0 0 0 0 0 0 12]
I would count the string of first 5 zeros. Then ignore the next 3 zeros 
because I only want to consider consecutive 4 zeros only. Then the next 
6 zeros are considered. And the total number of zeros become, 5 + 6 = 
11.

I have been to count the number of zeros in any string but not able to 
accumulate them to get the final answer. I would be much thankful if 
someone can guide me. I am attaching my module as well as testbench. 
Notice that the test bench reads 10 bit samples from a txt file, namely, 
'P281000BSR.txt', the test bench works fine, only the module is to be 
rectified.

According to my matlab code, the answer for this txt file should be 127 
in decimal.

Author: Lothar Miller (lkmiller) (Moderator)
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I'm doing VHDL and so I can't serve a solution, but I would do it this 
fairly easy way:
I would initially set a sum to 0 and I would set a counter to 0. And 
then I would walk through the data and increment the counter every 
step I get a 0. When the input data is not 0 then I would compare the 
counter with 4 and if its more than 4 then I would add the counter 
to the sum and reset the counter to 0.

: Edited by Moderator
Author: Lothar Miller (lkmiller) (Moderator)
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Lothar M. wrote:
> I'm doing VHDL and so I can't serve a solution
I must correct myself... ;-)


In Verilog this looks like that:
 module BSR(
   
   input wire clk,
   //input wire clk_enable,
   input wire reset,
   input signed [9:0] data_in,
   output reg [9:0] counter,
   output reg [9:0] acc   
   );
   always @ (posedge clk)
   begin
      if(reset)
      begin
         counter = 0;      
         acc <= 0;
      end
      
      else
      begin
         if (data_in == 0)
         begin
            counter = counter + 1'b1;
         end
         else
         begin
            if (counter > 2'b11) begin
               acc <= counter + acc;
            end
            counter = 0;
         end            
            
      end
   end
       
endmodule

: Edited by Moderator
Author: Usman Ashraf (Company: LUMS) (usmanashraf678)
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Dear Miller,

I must say, you are genius. I was so confused about the implementation 
in Verilog. Thanks so much. I would be great if you would clarify using 
the blocking assignment for counter. Is this a good practice? How does 
it affect our design? I was trying to implement the algorithm with 
non-blocking (<=) statements only.

Thanks again.

Author: Lothar Miller (lkmiller) (Moderator)
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Usman A. wrote:
> I would be great if you would clarify using the blocking assignment for
> counter. Is this a good practice?
As I said: usually I do VHDL and so I simply don't know, but simulation 
looks fine...  ;-)

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