Hi All I was building a complex multiplier into my HDL code, and noticed it was beginning to look like the Xilinx block. Looking at the documentation of the latter, I notice there is a latency overhead associated with blocking behaviour. This would appear to be due to buffering. I offer an unbuffered version here for criticism, it has a latency overhead, in blocking mode, of zero, but note, is still a piece of brainstorming, not validated IP. I created it out of a general curiosity about blocking in a system with inputs, a pipelined function, and an output. The clock for the processing engine is enabled only if both inputs have tready asserted. An input is ready only if the output tready signal is asserted, and all inputs have valid data. The output tvalid signal is forwarded from one of the inputs, the logic ensuring that these are all identical. It is maintained, until acknowledged by an output tready. Protocol failure will break this block, inputs must have assured tvalid behaviour. Best regards Geoff