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Forum: FPGA, VHDL & Verilog Quartus II connect bus to 2D array-input of block


Author: C17 (Guest)
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Hi everyone

My problem may be resolved easily, but I couldn't figure out how to do 
this and didn't find any solution on google.

I have a block with a 12 x 16 bit array input:
type datain is array (11 downto 0) of std_logic_vector(15 downto 0);

This block is responsible for logging system variables. So it should be 
possible to connect an arbitrary 16 bit std_logic_vector to one of the 
12 input rows of the block.

My problem is, I couldn't find out how to connect one of those signals 
to one of the inputs of the block. Connecting single bits to a bus is 
easy, as you can just take a WIRE element and connect vld_bit to 
input[1]. But how do I connect current[15..0] to input[1][15..0] ? Is 
there something like a WIRE block for buses?

A minimal example of my problem is attached.

Thank you a lot.

Kind regards,
AP

Author: Duke Scarring (Guest)
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C17 wrote:
> But how do I connect current[15..0] to input[1][15..0] ?

How about this?
...
type datain_t is array (11 downto 0) of std_logic_vector(15 downto 0);

signal input   : datain_t;
signal current : std_logic_vector(15 downto 0);

begin
...
input(1) <= current;
...
end;

Duke

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