Pablo P. wrote:
> Unfortunately the standard of VHDL unable me to have "one signal" driven
> by two others.
Its not a restriction of VHDL, it is a restriction of the hardware. Draw
a sketch how you would wire your problem with registers, RAMs and
multiplexers in hardware. Then use VHDL to describe that drawing. There
will be no multiple driven signal in that description.
> An array is treated as one object
Thats not correct. You easily can write one bit in an array and read the
very next bit. Its only a matter of hardware wiring.
> I would like to do perform two operations in parallel: -loading data by
> DMA to the 3rd and 4th cell -and in the same time 1st and 2nd cell
A big "array of vectors" usually is a memory block. And its fairly
unusual to write on a memory cell from two sources concurrently. Or even
to address four memory cells at the very same time (at least I don't
know a RAM with 4 adress-data-ports, best you can get is a dual-port or
a three-port RAM).
> I would like to do perform two operations in parallel: -loading data by
> DMA to the 3rd and 4th cell -and in the same time 1st and 2nd cell would
> be a subject to "addition" operation between other interfaced unit with
> which contain the required data for the calculation.
Thats obviously no problem if you don't use a memory block to locate the
"cells".
> after that 3rd and 4th are the ones on which the caluclation is
> performed
> and 5th and 6th is loaded from memory
> and so on...
I can't se a problem here, and of course the only solution is a
multiplexer. This multiplexer will rapidly become a huge and slow
megamonstermultiplexer when the number of cells increase.
So the problem here is not VHDL itself. The problem is that you do some
"programming in VHDL" but you do not describe hardware as the HDL part
of VHDL suggests.