# Forum: FPGA, VHDL & Verilog An array of std_logic_vector driven by two processes.

 Author: Pablo P. (Company: student) (pawel089) Posted on: 2018-02-01 02:43

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Hello,

I have an idea for a pipelined execution on an array. The calculations
are performed between certain cells of the array and the data in these
cells is replaced after the calculation. The data in one cell is the
result of addition of the cell itself (loaded by DMA) and an external
data from another unit. I would like to have the capability of having
influence on certain cells of the array from 2 different processes, the
conditions will prevent any unwanted situation.

Unfortunately the standard of VHDL unable me to have "one signal" driven
by two others. I was wondering if an multiplexer would be a good
solution but we have a situation of many driving inputs into many
different cells. An array is treated as one object so it doesn't matter
if we have two processes having influence on one cell or many different
(what it fact wouldnt generate any collisions) I receive error that one
signal cannot be driven by many processes.

I would like to do perform two operations in parallel:
-and in the same time 1st and 2nd cell would be a subject to "addition"
operation between other interfaced unit with which contain the required
data for the calculation.

after that 3rd and 4th are the ones on which the caluclation is
performed
and 5th and 6th is loaded from memory
and so on...

Did anybody ever struggled with similar problem?

Pablo

 Author: Lothar M. (lkmiller) (Moderator) Posted on: 2018-02-01 06:59

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Pablo P. wrote:
> Unfortunately the standard of VHDL unable me to have "one signal" driven
> by two others.
Its not a restriction of VHDL, it is a restriction of the hardware. Draw
a sketch how you would wire your problem with registers, RAMs and
multiplexers in hardware. Then use VHDL to describe that drawing. There
will be no multiple driven signal in that description.

> An array is treated as one object
Thats not correct. You easily can write one bit in an array and read the
very next bit. Its only a matter of hardware wiring.

> I would like to do perform two operations in parallel: -loading data by
> DMA to the 3rd and 4th cell -and in the same time 1st and 2nd cell
A big "array of vectors" usually is a memory block. And its fairly
unusual to write on a memory cell from two sources concurrently. Or even
to address four memory cells at the very same time (at least I don't
know a RAM with 4 adress-data-ports, best you can get is a dual-port or
a three-port RAM).

> I would like to do perform two operations in parallel: -loading data by
> DMA to the 3rd and 4th cell -and in the same time 1st and 2nd cell would
> be a subject to "addition" operation between other interfaced unit with
> which contain the required data for the calculation.
Thats obviously no problem if you don't use a memory block to locate the
"cells".

> after that 3rd and 4th are the ones on which the caluclation is
> performed
> and 5th and 6th is loaded from memory
> and so on...
I can't se a problem here, and of course the only solution is a
multiplexer. This multiplexer will rapidly become a huge and slow
megamonstermultiplexer when the number of cells increase.

So the problem here is not VHDL itself. The problem is that you do some
"programming in VHDL" but you do not describe hardware as the HDL part
of VHDL suggests.

 Author: Pablo P. (Company: student) (pawel089) Posted on: 2018-02-01 17:40

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Thank you very much for the answer, I have started to draw the schemes
of 4th port access to data and just have resigned from my solution when
I saw how complicated the multiplexers happened to be. Instead of that I
have just generated two-port-ram component from altera library. My
design will not be as optimal but at least will not take as much space,
hopefully.

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