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Forum: FPGA, VHDL & Verilog Counter that goes up to 9 and down


von Jason J. (Company: nope) (liad1234)


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hello im new to FPGA and ive been trying to make a 4 bits counter that 
counts up to 9 and goes down to 0 and then again and again with no 
success... so im asking for help for how to do it from anyone who can 
help!  thank you. this is what i have right now after some failed 
attempts.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity ElevatorCounter is
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port (Clock, reset: in std_logic;
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      Q            : out std_logic_vector (3 downto 0);
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    end entity;
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architecture arch_ElevatorCounter of ElevatorCounter is 
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begin 
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    process(clock, reset) 
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          variable tempQ : std_logic_vector(3 downto 0);
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  begin 
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      if Reset='0' then 
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        tempQ := "0000";
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    elsif rising_edge(clock) then 
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             tempQ :=tempQ + 1;    
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        if tempQ= "1001" then 
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          tempQ := tempQ - 1;
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            wait until tempQ := "0000";
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      end if;
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            if tempQ= "0000" then
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            tempQ := tempQ + 1;
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          wait until tempQ := "1001";
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          end if;  
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        end if; 
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      end if;
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    Q <= tempQ;
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  end process;
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end architecture;

: Edited by Moderator
von Donni (Guest)


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I would use a simple state machine with two states UP & DOWN. If tmp is 
9 set state to DOWN, if tmp is 0 or you have the reset set state to UP.

Then check the state and increment or decrement.

von Lothar M. (lkmiller) (Moderator)


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Jason J. wrote:
> hello im new to FPGA and ive been trying to make a 4 bits counter that
> counts up to 9 and goes down to 0 and then again and again with no success
What about simulating this piece of code?

> wait until...
This will not work in real life here. You are not "programming" with 
VHDL. Only about 10% of VHDL are synthesizeble. And those 10% must be 
used in a way the synthesizer understands it. The easiest way is to do 
it like others do it, the other way is to read the synthesizers manual.

> variable tempQ : std_logic_vector(3 downto 0);
I urge you NOT to use any variables for storing elements. Use signals 
instead!

von Lothar M. (lkmiller) (Moderator)


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My attempt would look like this:
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ElevatorCounter is
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  port (clock : in  std_logic;
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        floor : out std_logic_vector (3 downto 0));
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end entity;
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architecture arch_ElevatorCounter of ElevatorCounter is
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signal d : std_logic := '0'; -- direction 0=up, 1=down
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signal f : integer := 0;   -- start at the basement
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begin 
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  process begin 
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    wait until rising_edge(clock);
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    if d='0' then -- up
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      if f<9 then
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        f <= f+1;
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      else
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        d <= '1'; -- next: down
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        f <= f-1;
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      end if;
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    else          -- down
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      if f>0 then
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        f <= f-1;
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      else
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        d <= '0'; -- next: up
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        f <= f+1;
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      end if;
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    end if;
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  end process;
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  floor <= std_logic_vector(to_unsigned(f,4));
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end architecture;
The result looks fine that far...

: Edited by Moderator
von Jason J. (Company: nope) (liad1234)


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weird when i try to compile that code i get these errors... help?



Error (10500): VHDL syntax error at elevatorcounter.vhd(9) near text 
"end";  expecting an identifier ("end" is a reserved keyword), or 
"constant", or "file", or "signal", or "variable"
Error (10500): VHDL syntax error at elevatorcounter.vhd(15) near text 
"begin";  expecting an identifier ("begin" is a reserved keyword), or 
"constant", or "file", or "signal", or "variable"
Error: Quartus II 64-Bit Create Symbol File was unsuccessful. 2 errors, 
0 warnings

von Lothar M. (lkmiller) (Moderator)


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Jason J. wrote:
>  i get these errors... help?
What I get with XST is
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:
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:
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Final Register Report
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Macro Statistics
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# Registers              : 5
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 Flip-Flops              : 5
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:
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:
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Process "Synthesize - XST" completed successfully
And 5 registers is fine for the desing: 4 for the counter and 1 for the 
direction.

Same for Lattice synthesizing engine:
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:
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:
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####### Begin Area Report (ElevatorCounter)###########
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Number of register bits => 5 of 1604 (0 % )
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:
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:
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Done: completed successfully
Same here, so its pretty sure that the Altera toolchain will be able to 
synthesize that code.

> when i try to compile that code
Pls. attach your VHDL file. Maybe something went wrong with copying...

: Edited by Moderator
von Markus F. (mfro)


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Lothar M. wrote:
> Same here, so its pretty sure that the Altera toolchain will be able to
> synthesize that code.

sure it does:
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+---------------------------------------------------------------------------------+
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; Flow Summary                                                                    ;
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+------------------------------------+--------------------------------------------+
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; Flow Status                        ; Successful - Thu Dec 14 12:44:06 2017      ;
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; Quartus II 64-Bit Version          ; 13.1.4 Build 182 03/12/2014 SJ Web Edition ;
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; Revision Name                      ; ElevatorCounter                            ;
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; Top-level Entity Name              ; ElevatorCounter                            ;
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; Family                             ; Cyclone III                                ;
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; Device                             ; EP3C120F484C7                              ;
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; Timing Models                      ; Final                                      ;
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; Total logic elements               ; 8 / 119,088 ( < 1 % )                      ;
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;     Total combinational functions  ; 8 / 119,088 ( < 1 % )                      ;
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;     Dedicated logic registers      ; 5 / 119,088 ( < 1 % )                      ;
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; Total registers                    ; 5                                          ;
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; Total pins                         ; 5 / 284 ( 2 % )                            ;
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; Total virtual pins                 ; 0                                          ;
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; Total memory bits                  ; 0 / 3,981,312 ( 0 % )                      ;
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; Embedded Multiplier 9-bit elements ; 0 / 576 ( 0 % )                            ;
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; Total PLLs                         ; 0 / 4 ( 0 % )                              ;
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+------------------------------------+--------------------------------------------+

von Jason J. (Company: nope) (liad1234)


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it happens when i try to compile this piece of code. i attached it. 
weird for me

von Andreas S. (Company: Schweigstill IT) (schweigstill)


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The port definition in your entity contains at least two big mistakes. 
Why would you expect the toolchain to compile or synthesize it?

von Jason J. (Company: nope) (liad1234)


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I dont know because i didnt change much there it compiled it last time.. 
:(

von Andreas S. (Company: Schweigstill IT) (schweigstill)


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But I see THAT THERE ARE TWO MISTAKES. So you have to correct them. 
Probably you should take a formal VHDL specification in order to find 
out the right syntax.

von Lothar M. (lkmiller) (Moderator)


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Jason J. wrote:
> i didnt change much there it compiled it last time.. :(
So its kind of easy: the problem must be one of those few changes you 
made.

Jason J. wrote:
> it happens when i try to compile this piece of code. i attached it.
You simply must remove the errors reported by the toolchain. Start with 
that in line 9. Look how a port declaration must look like.
One hint: count all of the brackets. Match the opening brackets to the 
closing ones...

> weird for me
Its a little weird for me, that you don't find this little problem 
yourself by consulting a VHDL book or some code samples.

von Jason J. (Company: nope) (liad1234)


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yes my bad I've found the problem after looking at every line. Thank 
you!!

von John (Guest)


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>> ElevatorCounter.vhd
>> I dont know because i didnt change much there it compiled it last time..

I hope I'll never use this elevator accidentally. It might get stuck 
somewhere at 8.5 ...

von Jason J. (Company: nope) (liad1234)


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John wrote:
>>> ElevatorCounter.vhd
>>> I dont know because i didnt change much there it compiled it last time..
>
> I hope I'll never use this elevator accidentally. It might get stuck
> somewhere at 8.5 ...



LOOOOL probably hahhaah

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