Jason J. wrote:
> hello im new to FPGA and ive been trying to make a 4 bits counter that
> counts up to 9 and goes down to 0 and then again and again with no success
What about simulating this piece of code?

> wait until...
This will not work in real life here. You are not "programming" with 
VHDL. Only about 10% of VHDL are synthesizeble. And those 10% must be 
used in a way the synthesizer understands it. The easiest way is to do 
it like others do it, the other way is to read the synthesizers manual.

> variable tempQ : std_logic_vector(3 downto 0);
I urge you NOT to use any variables for storing elements. Use signals 
instead!

My attempt would look like this:

1

library ieee;

2

use ieee.std_logic_1164.all;

3

use ieee.numeric_std.all;

4

5

entity ElevatorCounter is

6

  port (clock : in  std_logic;

7

        floor : out std_logic_vector (3 downto 0));

8

end entity;

9

10

architecture arch_ElevatorCounter of ElevatorCounter is

11

12

signal d : std_logic := '0'; -- direction 0=up, 1=down

13

signal f : integer := 0;   -- start at the basement

14

15

begin 

16

17

  process begin 

18

    wait until rising_edge(clock);

19

    if d='0' then -- up

20

      if f<9 then

21

        f <= f+1;

22

      else

23

        d <= '1'; -- next: down

24

        f <= f-1;

25

      end if;

26

    else          -- down

27

      if f>0 then

28

        f <= f-1;

29

      else

30

        d <= '0'; -- next: up

31

        f <= f+1;

32

      end if;

33

    end if;

34

  end process;

35

36

  floor <= std_logic_vector(to_unsigned(f,4));

37

38

end architecture;

The result looks fine that far...

weird when i try to compile that code i get these errors... help?



Error (10500): VHDL syntax error at elevatorcounter.vhd(9) near text 
"end";  expecting an identifier ("end" is a reserved keyword), or 
"constant", or "file", or "signal", or "variable"
Error (10500): VHDL syntax error at elevatorcounter.vhd(15) near text 
"begin";  expecting an identifier ("begin" is a reserved keyword), or 
"constant", or "file", or "signal", or "variable"
Error: Quartus II 64-Bit Create Symbol File was unsuccessful. 2 errors, 
0 warnings

Jason J. wrote:
>  i get these errors... help?
What I get with XST is

1

:

2

:

3

4

Final Register Report

5

6

Macro Statistics

7

# Registers              : 5

8

 Flip-Flops              : 5

9

10

:

11

:

12

Process "Synthesize - XST" completed successfully

And 5 registers is fine for the desing: 4 for the counter and 1 for the 
direction.

Same for Lattice synthesizing engine:

1

:

2

:

3

4

####### Begin Area Report (ElevatorCounter)###########

5

Number of register bits => 5 of 1604 (0 % )

6

7

:

8

:

9

10

Done: completed successfully

Same here, so its pretty sure that the Altera toolchain will be able to 
synthesize that code.

> when i try to compile that code
Pls. attach your VHDL file. Maybe something went wrong with copying...

Lothar M. wrote:
> Same here, so its pretty sure that the Altera toolchain will be able to
> synthesize that code.

sure it does:

1

+---------------------------------------------------------------------------------+

2

; Flow Summary                                                                    ;

3

+------------------------------------+--------------------------------------------+

4

; Flow Status                        ; Successful - Thu Dec 14 12:44:06 2017      ;

5

; Quartus II 64-Bit Version          ; 13.1.4 Build 182 03/12/2014 SJ Web Edition ;

6

; Revision Name                      ; ElevatorCounter                            ;

7

; Top-level Entity Name              ; ElevatorCounter                            ;

8

; Family                             ; Cyclone III                                ;

9

; Device                             ; EP3C120F484C7                              ;

10

; Timing Models                      ; Final                                      ;

11

; Total logic elements               ; 8 / 119,088 ( < 1 % )                      ;

12

;     Total combinational functions  ; 8 / 119,088 ( < 1 % )                      ;

13

;     Dedicated logic registers      ; 5 / 119,088 ( < 1 % )                      ;

14

; Total registers                    ; 5                                          ;

15

; Total pins                         ; 5 / 284 ( 2 % )                            ;

16

; Total virtual pins                 ; 0                                          ;

17

; Total memory bits                  ; 0 / 3,981,312 ( 0 % )                      ;

18

; Embedded Multiplier 9-bit elements ; 0 / 576 ( 0 % )                            ;

19

; Total PLLs                         ; 0 / 4 ( 0 % )                              ;

20

+------------------------------------+--------------------------------------------+

it happens when i try to compile this piece of code. i attached it. 
weird for me

The port definition in your entity contains at least two big mistakes. 
Why would you expect the toolchain to compile or synthesize it?

I dont know because i didnt change much there it compiled it last time.. 
:(

But I see THAT THERE ARE TWO MISTAKES. So you have to correct them. 
Probably you should take a formal VHDL specification in order to find 
out the right syntax.

Jason J. wrote:
> i didnt change much there it compiled it last time.. :(
So its kind of easy: the problem must be one of those few changes you 
made.

Jason J. wrote:
> it happens when i try to compile this piece of code. i attached it.
You simply must remove the errors reported by the toolchain. Start with 
that in line 9. Look how a port declaration must look like.
One hint: count all of the brackets. Match the opening brackets to the 
closing ones...

> weird for me
Its a little weird for me, that you don't find this little problem 
yourself by consulting a VHDL book or some code samples.

yes my bad I've found the problem after looking at every line. Thank 
you!!

John wrote:
>>> ElevatorCounter.vhd
>>> I dont know because i didnt change much there it compiled it last time..
>
> I hope I'll never use this elevator accidentally. It might get stuck
> somewhere at 8.5 ...



LOOOOL probably hahhaah