EmbDev.net

Forum: FPGA, VHDL & Verilog Query regarding 32bits ALU design


Author: NIDHI K. (Company: STUDENT) (n_khanna)
Posted on:

Rate this post
0 useful
not useful
I want to implement 32bits alu on nexys4 ddr fpga board but there is an 
issue regarding I/O pins number board has total 16 input pins so i was 
tring to write the code as follow- but i am not getting the simulation 
results outputs are coming as unsigned
ibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu_32 is
port ( clk,reset : in std_logic;
          sel : in std_logic_vector(2 downto 0);
       a,b : in std_logic_vector(31 downto 0);
       y : out std_logic_vector(31 downto 0) );
end alu_32;

architecture Behavioral of alu_32 is
  --signal a : std_logic_vector(31 downto 0) ;
  --signal  a,b : std_logic_vector(31 downto 0);
  signal count1,count2 : std_logic_vector (1 downto 0);
  signal atemp, btemp ,atemp1, btemp1: std_logic_vector(15 downto 0);
  signal y1,y2  :std_logic_vector(31 downto 0);
  begin
process(clk)
begin
      if (reset='1')then
     y<="00000000000000000000000000000000";
     end if;
    if (rising_edge(clk)) then 
      if count1 ="11" then
      count1 <= "00";
      else 
      count1 <= count1 + 1;
      end if;
    end if;
        if  count1 = "00" then
       atemp <= y1(31 downto 16);
       elsif 
       count1 = "01" then
       btemp <= y1(15 downto 0);
       elsif
       count1 ="10" then
       a<= atemp & btemp;
     end if;
     
      if  count2 = "00" then
       atemp1 <= y2(31 downto 16);
       elsif 
       count2 = "01" then 
       btemp1 <= y2(15 downto 0);
       elsif 
       count2 ="10" then
       b<= atemp1 & btemp1;
     end if;   
end process;
PROCESS (sel)
begin
 case sel is
 when "001" => y <=  (a - b) ;
 when "010" => y <=  not (a) ;
 when "011" => y <=  (a xor  b) ;
 when "100" => y <=  (a + b) ;
 when "101" => y <=(a and b) ;
 when "110" => y <=  (a or b) ;
 when others => y <=  (a nand  b) ;
 End case ;
 end process ;
end Behavioral;
----------------------------------------------------------------
TESTBENCH 


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test32bit_vhd IS
END test32bit_vhd;

ARCHITECTURE behavior OF test32bit_vhd IS 

  -- Component Declaration for the Unit Under Test (UUT)
  COMPONENT alu32
  PORT(
    clk ,reset: IN std_logic;
    sel : IN std_logic_vector(2 downto 0);    
    a : INOUT std_logic_vector(31 downto 0);
    b : INOUT std_logic_vector(31 downto 0);      
    y : OUT std_logic_vector(31 downto 0)
    );
  END COMPONENT;

  --Inputs
  SIGNAL clk :  std_logic := '0';
  SIGNAL reset :  std_logic := '0';
  SIGNAL sel :  std_logic_vector(2 downto 0) := (others=>'0');

  --BiDirs
  SIGNAL a :  std_logic_vector(31 downto 0);
  SIGNAL b :  std_logic_vector(31 downto 0);

  --Outputs
  SIGNAL y :  std_logic_vector(31 downto 0);
  constant clkperiod : time := 100 ns;

BEGIN

  -- Instantiate the Unit Under Test (UUT)
  uut: alu32 PORT MAP(
    clk => clk,
    reset => reset,
    sel => sel,
    a => a,
    b => b,
    y => y
  );

  clk_process : process


  BEGIN

clk <= '0';
wait for clkperiod/2 ;
clk <= '1';
wait for clkperiod/2;
end process;

stimproces : process
begin 
    wait for 100 ns;
    wait for 50 ns;
    
    reset <= '1';
    
    
    wait for 100 ns;
    reset <= '0' ;
    
    wait for 100 ns;
    a <= "01011101010100111110000101100010";
    b <= "00111100101011111100111001100111";
    --enable <= '1';
    
    sel <= "001";
    
    wait for 200 ns;
    sel <= "010";
    
    wait for 200 ns;
    wait; -- will wait forever
  END PROCESS;

END;

PLZ tell me the mistake i am doing in writing the codes

: Edited by Moderator
Author: Lothar M. (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
NIDHI K. wrote:
> i was tring to write the code as follow
Pls read and follow the instructions above every edit box. Here a 
summary:
Reply
Rules — please read before posting
    Post long source code as attachment, not in the text
Formatting options
    [vhdl]VHDL code[/vhdl]

NIDHI K. wrote:
> PLZ tell me the mistake i am doing in writing the codes
What simulation result do you get and what did you expect?

>    if (reset='1')then
>       y<="00000000000000000000000000000000";
>    end if;
>    if (rising_edge(clk)) then ...
It is not possible to synthesize this, because its some kind of "clock 
sensitive despite reset" construct. I'm pretty sure you will not find 
such a piece of code elsewhere...

> but i am not getting the simulation results outputs are coming as
> unsigned
Do you 1. not get a result or 2. do you get an unsigned result?

> a : INOUT std_logic_vector(31 downto 0);
> b : INOUT std_logic_vector(31 downto 0);
Why the heck an inout here?
The components port must fit the entitys port.

> USE ieee.std_logic_unsigned.all;
> USE ieee.numeric_std.ALL;
Never ever use both of the packages together, because you may encouter 
strange errors due to double type definitions. I urge you to use only 
the numeric_std.

> PROCESS (sel)
> begin
In ths process sensitivity list the signals a and b are missing. That 
means your simulation is 1. wrong and 2. does not match the reality.


>        if  count1 = "00" then
>        atemp <= y1(31 downto 16);
>        elsif
>        count1 = "01" then
>        btemp <= y1(15 downto 0);
>        elsif
>        count1 ="10" then
>        a <= atemp & btemp;
This is kind of nonsense: splitting up a vector y1 and then 
concatenating it in three steps to the previous value. What is it good 
for?

> entity alu_32 is
> port ( clk,reset : in std_logic;
An Arithmetic Logic Unit usually does NOT have or need a clock. Why does 
yours?

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.