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Forum: FPGA, VHDL & Verilog Query regarding 32bits ALU design


von NIDHI K. (Company: STUDENT) (n_khanna)


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I want to implement 32bits alu on nexys4 ddr fpga board but there is an 
issue regarding I/O pins number board has total 16 input pins so i was 
tring to write the code as follow- but i am not getting the simulation 
results outputs are coming as unsigned
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ibrary IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity alu_32 is
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port ( clk,reset : in std_logic;
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          sel : in std_logic_vector(2 downto 0);
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       a,b : in std_logic_vector(31 downto 0);
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       y : out std_logic_vector(31 downto 0) );
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end alu_32;
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architecture Behavioral of alu_32 is
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  --signal a : std_logic_vector(31 downto 0) ;
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  --signal  a,b : std_logic_vector(31 downto 0);
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  signal count1,count2 : std_logic_vector (1 downto 0);
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  signal atemp, btemp ,atemp1, btemp1: std_logic_vector(15 downto 0);
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  signal y1,y2  :std_logic_vector(31 downto 0);
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  begin
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process(clk)
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begin
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      if (reset='1')then
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     y<="00000000000000000000000000000000";
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     end if;
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    if (rising_edge(clk)) then 
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      if count1 ="11" then
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      count1 <= "00";
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      else 
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      count1 <= count1 + 1;
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      end if;
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    end if;
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        if  count1 = "00" then
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       atemp <= y1(31 downto 16);
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       elsif 
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       count1 = "01" then
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       btemp <= y1(15 downto 0);
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       elsif
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       count1 ="10" then
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       a<= atemp & btemp;
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     end if;
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      if  count2 = "00" then
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       atemp1 <= y2(31 downto 16);
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       elsif 
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       count2 = "01" then 
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       btemp1 <= y2(15 downto 0);
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       elsif 
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       count2 ="10" then
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       b<= atemp1 & btemp1;
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     end if;   
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end process;
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PROCESS (sel)
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begin
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 case sel is
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 when "001" => y <=  (a - b) ;
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 when "010" => y <=  not (a) ;
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 when "011" => y <=  (a xor  b) ;
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 when "100" => y <=  (a + b) ;
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 when "101" => y <=(a and b) ;
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 when "110" => y <=  (a or b) ;
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 when others => y <=  (a nand  b) ;
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 End case ;
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 end process ;
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end Behavioral;
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----------------------------------------------------------------
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TESTBENCH 
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.all;
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USE ieee.numeric_std.ALL;
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ENTITY test32bit_vhd IS
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END test32bit_vhd;
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ARCHITECTURE behavior OF test32bit_vhd IS 
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  -- Component Declaration for the Unit Under Test (UUT)
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  COMPONENT alu32
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  PORT(
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    clk ,reset: IN std_logic;
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    sel : IN std_logic_vector(2 downto 0);    
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    a : INOUT std_logic_vector(31 downto 0);
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    b : INOUT std_logic_vector(31 downto 0);      
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    y : OUT std_logic_vector(31 downto 0)
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    );
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  END COMPONENT;
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  --Inputs
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  SIGNAL clk :  std_logic := '0';
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  SIGNAL reset :  std_logic := '0';
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  SIGNAL sel :  std_logic_vector(2 downto 0) := (others=>'0');
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  --BiDirs
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  SIGNAL a :  std_logic_vector(31 downto 0);
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  SIGNAL b :  std_logic_vector(31 downto 0);
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  --Outputs
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  SIGNAL y :  std_logic_vector(31 downto 0);
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  constant clkperiod : time := 100 ns;
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BEGIN
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  -- Instantiate the Unit Under Test (UUT)
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  uut: alu32 PORT MAP(
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    clk => clk,
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    reset => reset,
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    sel => sel,
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    a => a,
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    b => b,
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    y => y
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  );
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  clk_process : process
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  BEGIN
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clk <= '0';
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wait for clkperiod/2 ;
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clk <= '1';
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wait for clkperiod/2;
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end process;
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stimproces : process
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begin 
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    wait for 100 ns;
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    wait for 50 ns;
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    reset <= '1';
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    wait for 100 ns;
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    reset <= '0' ;
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    wait for 100 ns;
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    a <= "01011101010100111110000101100010";
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    b <= "00111100101011111100111001100111";
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    --enable <= '1';
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    sel <= "001";
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    wait for 200 ns;
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    sel <= "010";
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    wait for 200 ns;
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    wait; -- will wait forever
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  END PROCESS;
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END;

PLZ tell me the mistake i am doing in writing the codes

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)


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NIDHI K. wrote:
> i was tring to write the code as follow
Pls read and follow the instructions above every edit box. Here a 
summary:
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NIDHI K. wrote:
> PLZ tell me the mistake i am doing in writing the codes
What simulation result do you get and what did you expect?

>    if (reset='1')then
>       y<="00000000000000000000000000000000";
>    end if;
>    if (rising_edge(clk)) then ...
It is not possible to synthesize this, because its some kind of "clock 
sensitive despite reset" construct. I'm pretty sure you will not find 
such a piece of code elsewhere...

> but i am not getting the simulation results outputs are coming as
> unsigned
Do you 1. not get a result or 2. do you get an unsigned result?

> a : INOUT std_logic_vector(31 downto 0);
> b : INOUT std_logic_vector(31 downto 0);
Why the heck an inout here?
The components port must fit the entitys port.

> USE ieee.std_logic_unsigned.all;
> USE ieee.numeric_std.ALL;
Never ever use both of the packages together, because you may encouter 
strange errors due to double type definitions. I urge you to use only 
the numeric_std.

> PROCESS (sel)
> begin
In ths process sensitivity list the signals a and b are missing. That 
means your simulation is 1. wrong and 2. does not match the reality.


>        if  count1 = "00" then
>        atemp <= y1(31 downto 16);
>        elsif
>        count1 = "01" then
>        btemp <= y1(15 downto 0);
>        elsif
>        count1 ="10" then
>        a <= atemp & btemp;
This is kind of nonsense: splitting up a vector y1 and then 
concatenating it in three steps to the previous value. What is it good 
for?

> entity alu_32 is
> port ( clk,reset : in std_logic;
An Arithmetic Logic Unit usually does NOT have or need a clock. Why does 
yours?

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