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Forum: FPGA, VHDL & Verilog Combinatorial logic


Author: Julian Mortimer (Company: Relevant Technologies Ltd) (geoffreym)
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Hello

I am now well into a design, and in testing it seems to work, the timing 
reports are good, and so on. But I strongly suspect te immense power of 
ignorance is helping me. The design is large, a Zynq 7045 will be 
congested, by the time it is all put together.

My question, where is it safe, and where is it not safe, to use 
combinatorial logic, in a piece of user-designed IP?

Many thanks to anyone who replies,
Geoff

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