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Forum: FPGA, VHDL & Verilog the verilog code occupies the hole resources


Author: Alireza S. (shavakandi)
Posted on:

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hi
I have written this code for my university project
and I have problem with it
I'd be excited if anyone could help me
the code uses hole resources of the FPGA for nothing
the part of the code that makes this problem is given bellow:
the problem is with assigning the input to the constant and giving it to
the predefined module .

module mojo_top(
    input clk,
    input rst_n,
    input show,
    input[3:0] data,
   output [6:0] fourth, third, second, first
    );
wire [127:0] key1;
wire[127:0] data1;
assign data1={data,124'h3243f6a8885a308d313198a2e037073};

aescipher 
u1(.clk(clk),.datain(data1),.key(128'h3243f6a8885a308d313198a2e0370733), 
.dataout(tempout));

Author: Lothar M. (lkmiller) (Moderator)
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What FPGA?
And what is aescipher?

Author: Alireza S. (shavakandi)
Posted on:
Attached files:

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the FPGA is Spartan6 and
aescipher is a module that is designed in another part of the code and 
is used in this part

Author: Alireza S. (shavakandi)
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I  sent the hole code in a .rar file attached to the previous post
the mojo top.v is my top module and I want  it to be edited like this
:
assign data1={data,124'h3243f6a8885a308d313198a2e037073};
assign key1={key,124'h3243f6a8885a308d313198a2e037073};
aescipher u1(.clk(clk),.datain(data1),.key(key1),.dataout(tempout));
but that problem that I mentioned will occur.

: Edited by User

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