the verilog code occupies the hole resources

hi
I have written this code for my university project
and I have problem with it
I'd be excited if anyone could help me
the code uses hole resources of the FPGA for nothing
the part of the code that makes this problem is given bellow:
the problem is with assigning the input to the constant and giving it to
the predefined module .

module mojo_top(
    input clk,
    input rst_n,
    input show,
    input[3:0] data,
   output [6:0] fourth, third, second, first
    );
wire [127:0] key1;
wire[127:0] data1;
assign data1={data,124'h3243f6a8885a308d313198a2e037073};

aescipher 
u1(.clk(clk),.datain(data1),.key(128'h3243f6a8885a308d313198a2e0370733), 
.dataout(tempout));