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Forum: FPGA, VHDL & Verilog Is this nonesense?


Author: Julian Mortimer (Company: Relevant Technologies Ltd) (geoffreym)
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Hi

I have multiple clocked processes, all of which must access the same 
resources in my ip block. I often end up with something like this:
process(ps_reset_cir_b, reset_cir_cmd_rqst, reset_cir_cmd_out, 
        ps_init_cir_b,  init_cir_cmd_rqst,  init_cir_cmd_out,  init_cir_arg_out, 
        ps_rx_row_b,    rx_row_cmd_rqst,    rx_row_cmd_out,     
        ps_tx_max_b,    tx_max_cmd_rqst,    tx_max_cmd_out,                     tx_max_tready,
        ps_tx_cir_b,    tx_cir_cmd_rqst,    tx_cir_cmd_out,    tx_cir_arg_out,  tx_cir_tready,
        ps_wr_bram_b,   wr_bram_cmd_rqst,   wr_bram_cmd_out,   wr_bram_arg_out, 
        ps_rd_bram_b,   rd_bram_cmd_rqst,   rd_bram_cmd_out,   rd_bram_arg_out, rd_bram_tready,
        ps_wr_reg_b,    wr_reg_cmd_rqst,    wr_reg_cmd_out,    wr_reg_arg_out, 
        ps_rd_reg_b,    rd_reg_cmd_rqst,    rd_reg_cmd_out,    rd_reg_arg_out,  rd_reg_tready
  )
begin
  if (ps_reset_cir_b = '1') then 
    s_axis_cir_tready      <= '0';
    cmd_rqst               <= reset_cir_cmd_rqst;   
    cmd_out                <= reset_cir_cmd_out;    
    arg_out                <= (others=>'0');    
  elsif (ps_init_cir_b = '1') then  
    s_axis_cir_tready      <= '0';
    cmd_rqst               <= init_cir_cmd_rqst;    
    cmd_out                <= init_cir_cmd_out;     
    arg_out                <= init_cir_arg_out;     
  elsif (ps_rx_row_b = '1') then
    s_axis_cir_tready      <= '0';
    cmd_rqst               <= rx_row_cmd_rqst;      
    cmd_out                <= rx_row_cmd_out;       
    arg_out                <= (others=>'0');       
  elsif (ps_tx_max_b = '1') then
    s_axis_cir_tready      <= tx_max_tready;
    cmd_rqst               <= tx_max_cmd_rqst;      
    cmd_out                <= tx_max_cmd_out;       
    arg_out                <= (others=>'0');       
  elsif (ps_tx_cir_b = '1') then
    s_axis_cir_tready      <= tx_cir_tready;
    cmd_rqst               <= tx_cir_cmd_rqst;      
    cmd_out                <= tx_cir_cmd_out;       
    arg_out                <= tx_cir_arg_out;       
  elsif (ps_wr_bram_b = '1') then
    s_axis_cir_tready      <= '0';
    cmd_rqst               <= wr_bram_cmd_rqst;     
    cmd_out                <= wr_bram_cmd_out;      
    arg_out                <= wr_bram_arg_out;      
  elsif (ps_rd_bram_b = '1') then
    s_axis_cir_tready      <= rd_bram_tready;
    cmd_rqst               <= rd_bram_cmd_rqst;     
    cmd_out                <= rd_bram_cmd_out;      
    arg_out                <= rd_bram_arg_out;      
  elsif (ps_wr_reg_b = '1') then
    s_axis_cir_tready      <= '0';
    cmd_rqst               <= wr_reg_cmd_rqst;  
    cmd_out                <= wr_reg_cmd_out;   
    arg_out                <= wr_reg_arg_out;   
  elsif (ps_rd_reg_b = '1') then
    s_axis_cir_tready      <= rd_reg_tready;
    cmd_rqst               <= rd_reg_cmd_rqst;  
    cmd_out                <= rd_reg_cmd_out;   
    arg_out                <= rd_reg_arg_out;
  else
    s_axis_cir_tready      <= '0';
    cmd_rqst               <= (others=>'0');  
    cmd_out                <= (others=>'0');  
    arg_out                <= (others=>'0');
  end if;   
end process;

Does this look silly? The various bits indicate the process which is 
accessing the mux is active. When all processes are in the idle state, 
the final else is active. The various processes, in this case, are 
servicing requests from the host cpu. The signals on the left are 
interfaces, and each process must use some or all of these.

Best regards
Geoff

Author: Lothar Miller (lkmiller) (Moderator)
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Julian M. wrote:
> I have multiple clocked processes
I can't see absolutely no clock there...

> Does this look silly?
No, ist just the way to write the multiplexer in a process. You could do 
it as a concurrent descritpion also.

But the most easy way would be: use VHDL-2008 and write process(all).

Then you could shorten it further on by using default values instead of 
the last "else":
process(all)
begin
  s_axis_cir_tready      <= '0';
  cmd_rqst               <= (others=>'0');  
  cmd_out                <= (others=>'0');  
  arg_out                <= (others=>'0');
  if (ps_reset_cir_b = '1') then 
    cmd_rqst               <= reset_cir_cmd_rqst;   
    cmd_out                <= reset_cir_cmd_out;    
  elsif (ps_init_cir_b = '1') then  
    cmd_rqst               <= init_cir_cmd_rqst;    
    cmd_out                <= init_cir_cmd_out;     
    arg_out                <= init_cir_arg_out;     
  elsif (ps_rx_row_b = '1') then
    cmd_rqst               <= rx_row_cmd_rqst;      
    cmd_out                <= rx_row_cmd_out;             
  elsif (ps_tx_max_b = '1') then
    s_axis_cir_tready      <= tx_max_tready;
    cmd_rqst               <= tx_max_cmd_rqst;      
    cmd_out                <= tx_max_cmd_out;       
  elsif (ps_tx_cir_b = '1') then
    s_axis_cir_tready      <= tx_cir_tready;
    cmd_rqst               <= tx_cir_cmd_rqst;      
    cmd_out                <= tx_cir_cmd_out;       
    arg_out                <= tx_cir_arg_out;       
  elsif (ps_wr_bram_b = '1') then
    cmd_rqst               <= wr_bram_cmd_rqst;     
    cmd_out                <= wr_bram_cmd_out;      
    arg_out                <= wr_bram_arg_out;      
  elsif (ps_rd_bram_b = '1') then
    s_axis_cir_tready      <= rd_bram_tready;
    cmd_rqst               <= rd_bram_cmd_rqst;     
    cmd_out                <= rd_bram_cmd_out;      
    arg_out                <= rd_bram_arg_out;      
  elsif (ps_wr_reg_b = '1') then
    cmd_rqst               <= wr_reg_cmd_rqst;  
    cmd_out                <= wr_reg_cmd_out;   
    arg_out                <= wr_reg_arg_out;   
  elsif (ps_rd_reg_b = '1') then
    s_axis_cir_tready      <= rd_reg_tready;
    cmd_rqst               <= rd_reg_cmd_rqst;  
    cmd_out                <= rd_reg_cmd_out;   
    arg_out                <= rd_reg_arg_out;
  end if;   
end process;

: Edited by Moderator
Author: Julian Mortimer (Company: Relevant Technologies Ltd) (geoffreym)
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Many thanks, I work alone, and still make some godawful blunders, having 
been doing this for about two years. Great fun, and a big paradigm shift 
from software, a background many will no doubt spot, due to my 
parentheses around conditions in if- statements.

Author: Julian Mortimer (Company: Relevant Technologies Ltd) (geoffreym)
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The clocked processes are using these resources, and of the usual sort. 
They are all state machines, which have an idle state in which they do 
nothing at all. So this is combinatorial logic in support of them. They 
are assumed to execute exclusively, and, as soon as they enter a state 
other than "???_IDLE" the bit is set.

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