Martin wrote:> It is negated R and negated S and flip flop based on NAND..
Maybe you can post the whole piece of homework?
And maybe its related to some excersie before it?
Those packages are absolutely needless here because no kind of any
calculation is done:
> use IEEE.STD_LOGIC_ARITH.ALL;> use IEEE.STD_LOGIC_UNSIGNED.ALL;
One word to your port list:
> r,s,clk : in STD_LOGIC;
clk? For what?
> It isnt that what she need...
Martin wrote:> can you help me?! Thanks!
Start with something and when encounter a specific problem, THEN ask.
But don't try that "who is doing my homework" story...
> q,qb : inout STD_LOGIC
That is no geood design practice.
Why the heck should q and qb have an input function? Use a buffer or
an out port.
Sir. We don't know how to program in VHDL. In our school we are only
learning to read what is in code and of what it is doing.. They want
from us to make Rnot Rnot flip flop with test bench that can be tested
in ModelSim Altera of Quartus 13.1 SP. I don't know what to do. With
outputs you are true.
Martin wrote:> I don't know what to do.
So first start with a empty "testbench" how it can be found everywhere
in books and on the internet: a VHDL file with an empty port list, in
which the DUT (device under test) is invoked as a component. Thenn add
some local signals, connect them to the flipflop ports and generate a
test pattern for the two inputs.
The whole test bench can be done in somewhat around 30 lines here,
because in the first step you don't need to verify the results, instead
just generate a waveform in the simulator.
It took me about 5 minutes, but it will help you no further when I
just give you that "testbench". So start with something and then we
BTW: I attached the corrected RS flipflop file. The arith package was
Hello there, thanks for reply, code working good and Waveform simulation
too, i tried to make test bench file, but i have problems with it.. It
draw something in Altera ModelSim. I zoomed to full but i got there only
"bars" from left to right full of green color.
I remember we had one homework months ago and there was something like
UUT in test bench and i wrote it to Assignments --> Settings --> Test
bench file but u dont know where take it now.
Actual VHDL TB code:
It is working! But i haven't edited test bench file. That time ago it
draws full lines, like 0 and 1 together with that "width" between them.
Now it looks good, But why it didn't automatically change values?
Yes, i click on stop and then Zoom. But values didn't change. What must
i change in TestBench file to make something like randomize after 50ns
etc.. I am very happy for that i alone wrote whole TestBench script.
Hey, what must i add to my code and how to make it correctly?!
Teacher told me that: I have RnotSnot, but it is negated RS. So i must
add to code RS too. For that i must make invertor.
r <= not rnot
s <= not snot
VHDL Compilation error: Error (10568): VHDL error at rs_nand.vhd(14):
can't write to interface object "r" of mode IN
i cannot negate it, because it is input. What now?
useIEEE.STD_LOGIC_1164.ALL;--pouzitie IEEE.STD_LOGIC pre vyuzitie STD_LOGIC FUNKCII
entityrs_nandis-- popis entity
Port(r,s,rnot,snot:inSTD_LOGIC;-- definovany port s log.vstupmi R, S
q,qb:outSTD_LOGIC);-- VYSTUPY Q QB
endrs_nand;--koniec popisu entity
signaltmp_q,tmp_qb:STD_LOGIC;-- vytvorenie logickych signalov tmp_q a tmp_qb
tmp_q<=snotNANDtmp_qb;-- popis signalu architektury na NAND hradle
tmp_qb<=rnotNANDtmp_q;-- popis signalu architektury na NAND hradle
q<=tmp_q;-- priradenie signalu tmp_q pre vystup q
qb<=tmp_qb;-- priradenie signalu tmp_qb pre vystup qb
Martin wrote:> can't write to interface object "r" of mode IN> i cannot negate it, because it is input. What now?
Use "brain 1.0" and start thinking. If thats way tooooooo difficult,
then simply place this lines to the correct position:
> I tried
> r,s,rnot,snot: in STD_LOGIC;
Take any beginners book about logic and have a look at the RS flipflop.
How many inputs does it have?
Right: two, in numbers 2.
Why does your RS flipflop have 4 inputs?
Martin wrote:> Altera ModelSim simulation didnt work!
Why? What errror messages do you get?
What do you expect? And what do you get instead?
Martin wrote:> VHDL file:> entity rs_nand is -- popis entity> TB file:> entity rs_nand is --opis entity
Why are there two entities with the same name?
To get things clear: in a beginners design in the testbench file there
is only 1 entity declaration. It is that one without ports.