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Forum: FPGA, VHDL & Verilog VHDL code for Rnon Snon (NAND) Flip flop


Author: Martin (Guest)
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Hello there, have somebody code for that? I want it for Quartus 
program!! Thanks a lot

Author: Peter (Guest)
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What is Rnon Snon? Even google doesn't know it.

Author: Martin (Guest)
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It is negated R and negated S and flip flop based on NAND..
I don't know how to realize it. I have sent that code to my teacher and 
she said: It isnt that what she need...
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rs_nand is
Port ( 
      r,s,clk : in  STD_LOGIC;
      q,qb : inout STD_LOGIC
      );
end rs_nand;


architecture rs_nand_arch of rs_nand is

signal temp1,temp2:STD_LOGIC;

component nand21
port(
      a,b: in STD_LOGIC;
      y:out STD_LOGIC
      );
end component;

begin
n1: nand21 port map(a=>r,b=>clk,y=>temp1);
n2: nand21 port map(a=>clk,b=>s,y=>temp2);
n3: nand21 port map(a=>temp1,b=>qb,y=>q);
n4: nand21 port map(a=>q,b=>temp2,y=>qb);

end rs_nand_arch;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity nand21 is
Port ( 
         a,b : in  STD_LOGIC;
         y : out  STD_LOGIC
      );
end nand21;

architecture nand_arch of nand21 is
begin
y <= a nand b;
end nand_arch;

Author: -gb- (Guest)
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Like here https://www.elektronik-kompendium.de/sites/dig/0209302.htm in 
the Picture (RS-FlipFlop)?

Author: Lothar Miller (lkmiller) (Moderator)
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Martin wrote:
> It is negated R and negated S and flip flop based on NAND..
Maybe you can post the whole piece of homework?
And maybe its related to some excersie before it?

Those packages are absolutely needless here because no kind of any 
calculation is done:
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;

One word to your port list:
> r,s,clk : in  STD_LOGIC;
clk? For what?


> It isnt that what she need...
Thats all?

Author: Martin (Guest)
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Hey there, i got code.. Now i want testbench for it.. can you help me?! 
Thanks!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rs_nand is
Port ( 
      r,s: in  STD_LOGIC;
      q,qb : inout STD_LOGIC
      );
end rs_nand;


architecture rs_nand_arch of rs_nand is

signal tmp_q, tmp_qb : STD_LOGIC;

begin
tmp_q <= s NAND tmp_qb;
tmp_qb <= r NAND tmp_q;

q <= tmp_q;
qb <= tmp_qb;

end rs_nand_arch;

Author: Lothar Miller (lkmiller) (Moderator)
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Martin wrote:
> can you help me?! Thanks!
For sure.
Start with something and when encounter a specific problem, THEN ask.
But don't try that "who is doing my homework" story...

> q,qb : inout STD_LOGIC
That is no geood design practice.
Why the heck should q and qb have an input function? Use a buffer or 
an out port.

: Edited by Moderator
Author: Martin (Guest)
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Sir. We don't know how to program in VHDL. In our school we are only 
learning to read what is in code and of what it is doing.. They want 
from us to make Rnot Rnot flip flop with test bench that can be tested 
in ModelSim Altera of Quartus 13.1 SP. I don't know what to do. With 
outputs you are true.

Author: Lothar Miller (lkmiller) (Moderator)
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Martin wrote:
> I don't know what to do.
So first start with a empty "testbench" how it can be found everywhere 
in books and on the internet: a VHDL file with an empty port list, in 
which the DUT (device under test) is invoked as a component. Thenn add 
some local signals, connect them to the flipflop ports and generate a 
test pattern for the two inputs.
The whole test bench can be done in somewhat around 30 lines here, 
because in the first step you don't need to verify the results, instead 
just generate a waveform in the simulator.

It took me about 5 minutes, but it will help you no further when I 
just give you that "testbench". So start with something and then we 
discuss.

BTW: I attached the corrected RS flipflop file. The arith package was 
unnecessary also...

: Edited by Moderator
Author: Martin (Guest)
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Hello there, thanks for reply, code working good and Waveform simulation 
too, i tried to make test bench file, but i have problems with it.. It 
draw something in Altera ModelSim. I zoomed to full but i got there only 
"bars" from left to right full of green color.
I remember we had one homework months ago and there was something like 
UUT in test bench and i wrote it to Assignments --> Settings --> Test 
bench file but u dont know where take it now.
Actual VHDL TB code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity rs_nand is
   port(r, s : in std_logic;
           q, qb : out std_logic);
end rs_nand;

architecture rs_nand_arch of rs_nand is
signal tmp_q, tmp_qb : STD_LOGIC;
begin
  tmp_q  <= s NAND tmp_qb;
  tmp_qb <= r NAND tmp_q;

  q  <= tmp_q;
  qb <= tmp_qb;
end rs_nand_arch;
--------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity rs_nand_tb is
end rs_nand_tb ;
architecture tb of rs_nand_tb  is
   component rs_nand is
      port(r, s : in std_logic;
             q, qb : out std_logic);
   end component;
   -------------
   signal r, s, q, qb : std_logic;
   -------------
begin
 mapping: rs_nand port map(r, s, q, qb);

 process
   
 begin
 -------------TEST 1
   s <= '0';
   r <= '0';
   wait for 10 ns;
   assert(q = '1') report "Error 1"  severity error;
   assert(qb = '1');
  ----------TEST 2
   s <= '0';
   r <= '1';
   wait for 10 ns;
   assert(q = '1');
  assert(qb = '0');
   ----------TEST 3
   s <= '1';
   r <= '0';
   wait for 10 ns;
   assert(q = '0');
  assert(qb = '1');
  ----------TEST 4
   s <= '1';
   r <= '1';
   wait for 10 ns;
   assert(q = q);
  assert(qb = not q);
   
    end process;
end tb;
configuration cfg_tb of rs_nand_tb is
   for tb
   end for;
end cfg_tb;

Author: Lothar Miller (lkmiller) (Moderator)
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Martin wrote:
> It draw something
A screenshot of that "something" would be nice...

Author: Martin (Guest)
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It is working! But i haven't edited test bench file. That time ago it 
draws full lines, like 0 and 1 together with that "width" between them. 
Now it looks good, But why it didn't automatically change values?

Author: Martin (Guest)
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Again something bad happened. I click on Zoom full and nothing 
happening.

Author: Lothar Miller (lkmiller) (Moderator)
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Martin wrote:
> It is working!
You are very right. The simulator is running. Try hitting the STOP 
button. Maybe then the scren is updated...

Author: Martin (Guest)
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Yes, i click on stop and then Zoom. But values didn't change. What must 
i change in TestBench file to make something like randomize after 50ns 
etc.. I am very happy for that i alone wrote whole TestBench script.

Author: Lothar Miller (lkmiller) (Moderator)
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I do not know whats going wrong with ModelSim, but your files are doing 
as expected on ISIM...

Author: Duke Scarring (Guest)
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The files work perfectly in modelsim too:
$ vcom nand.vhd
vcom nand.vhd
Model Technology ModelSim SE-64 vcom 10.6c Compiler 2017.07 Jul 26 2017
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity rs_nand
-- Compiling architecture rs_nand_arch of rs_nand
-- Compiling entity rs_nand_tb
-- Compiling architecture tb of rs_nand_tb
-- Compiling configuration cfg_tb
-- Loading entity rs_nand_tb
-- Loading architecture tb of rs_nand_tb
-- Loading entity rs_nand
Errors: 0, Warnings: 0

$ vsim -gui rs_nand_tb

vsim> add wave *
vsim> run 60 ns
Use the zoom fit function in wave window to show everything.

Duke

Author: Martin (Guest)
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Working! THanks a lot. Problem was i have it so much Zoomed in... Thanks 
a lot for your help!

Author: Martin (Guest)
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Hey, what must i add to my code and how to make it correctly?!
Teacher told me that: I have RnotSnot, but it is negated RS. So i must 
add to code RS too. For that i must make invertor.
I tried
r <= not rnot
s <= not snot
VHDL Compilation error: Error (10568): VHDL error at rs_nand.vhd(14): 
can't write to interface object "r" of mode IN

i cannot negate it, because it is input. What now?
library IEEE; --kniznica IEEE
use IEEE.STD_LOGIC_1164.ALL; --pouzitie IEEE.STD_LOGIC pre vyuzitie STD_LOGIC FUNKCII

entity rs_nand is -- popis entity
Port (r,s,rnot,snot: in  STD_LOGIC; -- definovany port s log.vstupmi R, S
      q,qb : out STD_LOGIC); -- VYSTUPY Q QB
end rs_nand; --koniec popisu entity

architecture rs_nand_arch of rs_nand is --popis architektury

signal tmp_q, tmp_qb : STD_LOGIC; -- vytvorenie logickych signalov tmp_q a tmp_qb

begin
r <= not rnot;
s <= not snot;
  tmp_q  <= snot NAND tmp_qb; -- popis signalu architektury na NAND hradle
  tmp_qb <= rnot NAND tmp_q; -- popis signalu architektury na NAND hradle

  q  <= tmp_q; -- priradenie signalu tmp_q pre vystup q
  qb <= tmp_qb; -- priradenie signalu tmp_qb pre vystup qb
end rs_nand_arch; --koniec popisu architektury

Author: Lothar Miller (lkmiller) (Moderator)
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Martin wrote:
> can't write to interface object "r" of mode IN
>  i cannot negate it, because it is input. What now?
Use "brain 1.0" and start thinking. If thats way tooooooo difficult, 
then simply place this lines to the correct position:
Port (rnot,snot: in  STD_LOGIC;
...
signal r,s : std_logic;
...
r <= not rnot;
s <= not snot;

> I tried
Bad idea.

> r,s,rnot,snot: in  STD_LOGIC;
Take any beginners book about logic and have a look at the RS flipflop.
How many inputs does it have?
Right: two, in numbers 2.
Why does your RS flipflop have 4 inputs?

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