Forum: FPGA, VHDL & Verilog Artix-7 SPI (x4) bitstream does not work for SelectMAP (x16)

von St. D. (st_d)

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Dear Xilinx experts!

we are experiencing a strange case here, about which we could not see 
any clue @ug470 (Configuration User Guide)

SPI (x4 master) bitstream does not work for SelectMAP (x16 slave) 
configuration interface.

Our SelectMAP configuration state machine is designed within another 
FPGA and it works well if the bitstream is generated with
set_property CONFIG_MODE                                 S_SELECTMAP16 [current_design]
However, a bitstream generated with these settings
set_property CONFIG_MODE                                         SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH                           4 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE                            66 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE                        YES [current_design]
does not work, although the bit order & the header part (Bus Width 
Detection Pattern, Sync Word, etc.) looks the same!

What could be the reason? Any ideas are very much appreciated...

von Duke Scarring (Guest)

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Did you try already a lower configrate?

von St. D. (st_d)

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Thanks for the reply!

I think BITSTREAM.CONFIG.CONFIGRATE must be relevant only to SPI master 
mode and our SPI mode configuration works pretty stable at 66MHz (Yes, 
we have also an SPI flash connected to FPGA, I forgot to mention above).

For Slave SelectMAP, the configuration clock is input to the Artix-7 and 
it is currently set to 55MHz, which also correctly work as long as the 
SelectMAP state machine (on the other FPGA) uses a bitstream 
specifically generated with CONFIG_MODE S_SELECTMAP16.

Our intention is to be able to use a single bitstream for both modes.

Other way around (if we use the SelectMAP bitstream for SPI) it actually 
works. But it is very very slow (x1 at ~3MHz).

: Edited by User


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