Dear Xilinx experts!
we are experiencing a strange case here, about which we could not see
any clue @ug470 (Configuration User Guide)
SPI (x4 master) bitstream does not work for SelectMAP (x16 slave)
Our SelectMAP configuration state machine is designed within another
FPGA and it works well if the bitstream is generated with
set_property CONFIG_MODE S_SELECTMAP16 [current_design]
However, a bitstream generated with these settings
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
does not work, although the bit order & the header part (Bus Width
Detection Pattern, Sync Word, etc.) looks the same!
What could be the reason? Any ideas are very much appreciated...