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Forum: FPGA, VHDL & Verilog test bench for digitAL PI controller


Author: Rock B. (rocko445)
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Hello, i am trying to build a test bench for a PI conntroller based on 
the attached article.

whole code is playing with coefficient for the  last line.
how do you recooment to represent the coefficients in the testbench?

Thanks
always #((t0-vctl*kphi)/2) vco<=~vco;

module loop_filter(t0,clk,integral,proportional,filt_i,filt_p,vtcl,kptl,vtcl,vco);

input t0,smpclk,integral,proportional,filt_i,filt_p,vtcl,kptl,vtcl;
output vco;

reg integral=4'b0;
reg proportional=4'b0;

always @(posedge smpclk)
begin
if (pdup==1'b1) begin
  integral=integral+filt_i;
  proportional=filt_p;
  end
  else if (pdup==1'b0)
  begin
  integral=integral-filt_i;  
  proportional=-filt_p;
  end
  else begin
         proportional=0;
  end
  
always #((t0-vctl*kphi)/2) vco<=~vco;
end
endmodule

: Edited by User

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