Help in vhdl project

Bozidar K. wrote:
> I got some kind of error: "Can't use Anode_Active same time in 2
> processes".
> Did anyone have a similar problem?
Yes, everybody who tries to assign a value to one and the same signal 
from two processes.

Have a look for "multiple drivers vhdl" to find thousands of similar 
problems...

BTW: pls attach *.vhdl files, not *.txt files. You will find some magic 
named syntax highlighting... ?

Meanwhile I had the time to peek into your code and one thing in 
advance:

1

  if (temp>=nfCLK/2) then

2

    clk_o<=not clk_o;

This ist not the proper way to generate clocks in FPGAs. Have a look for 
a strategy named "Clock Enable"...

Bozidar K. wrote:
> I got some kind of error
When I synthesize those files with Xilinx ISE I get:

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Process "Synthesize - XST" completed successfully

But the simulation shows: those two frequency dividers are working, but 
nothing else is going on.
A closer look turns up: the counter led_activating is XX throughout 
resulting in presenting the "when others" value at the "Anode_Active" 
and "LED".

Try it with initializing the counter:

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signal led_activating: std_logic_vector (1 downto 0) := "00";

Then the simulation runs like it should...